Storage array supporting multi-thread access

Abstract

Systems, methods, and circuitries are provided for supporting multiple concurrent thread access to a storage array. In one example, a storage array includes a plurality of storage devices each divided into at least N subdivisions. A volume includes a set of subdivisions including a subdivision in each of M different storage devices. Memory management circuitry receives first data and second data for storing in the storage array and selects a first volume for storing the first data and a second volume for storing the second data. The second volume includes a different set of subdivisions than the first volume. The processor uses a first set of processor threads to process and store the first data in the first volume and uses a second set of processor threads to, concurrent with the processing and storing of the first data, process and store the second data in the second volume.

What is claimed is: 
     
       1. A method, comprising:
 receiving first data and second data for storing in a storage array, wherein the storage array comprises a plurality of storage devices, further wherein each storage device has been divided into at least N subdivisions; 
 selecting a first volume for storing the first data, wherein a volume comprises a set of subdivisions including a subdivision in each of M different storage devices in the plurality of storage devices; 
 selecting a second volume for storing the second data, wherein the second volume comprises a different set of subdivisions than the first volume; 
 with a first set of processor threads:
 processing the first data for storage in the storage array; and 
 storing the first data in the first volume; 
 
 with a second set of processor threads different from the first set of processor threads:
 concurrent with the processing and storing of the first data, processing the second data for storage in the storage array; and 
 storing the second data in the second volume. 
 
 
     
     
       2. The method of  claim 1 , wherein each subdivision comprises a namespace. 
     
     
       3. The method of  claim 1 , wherein each subdivision in each volume comprises a same amount of memory. 
     
     
       4. The method of  claim 3 , wherein each subdivision on each storage device comprises a same amount of memory. 
     
     
       5. The method of  claim 1 , further comprising:
 selecting a third set of processor threads in response to receiving a request to access the first data; and 
 using the third set of processor threads to access the first data. 
 
     
     
       6. The method of  claim 5 , comprising selecting the first set of processor threads as the third set of processor threads, such that the first set of processor threads is statically assigned for access the first data. 
     
     
       7. The method of  claim 5 , comprising selecting the third set of processor threads based on a current operating condition of the storage array. 
     
     
       8. The method of  claim 1 , comprising:
 processing the first data to generate first erasure coding data; 
 storing the first erasure coding data in the first volume; 
 processing the second data to generate second erasure coding data; and 
 storing the second erasure coding data in the second volume. 
 
     
     
       9. The method of  claim 8 , wherein the first erasure coding data and the second erasure coding data comprises XOR erasure coding data. 
     
     
       10. The method of  claim 8 , wherein the first erasure coding data and the second erasure coding data comprises P/Q parity erasure coding data. 
     
     
       11. The method of  claim 8  wherein the first erasure coding data and the second erasure coding data comprises Reed-Solomon erasure coding data. 
     
     
       12. The method of  claim 1 , comprising:
 with the first set of processor threads:
 separating the first data into x stripes; 
 generating y sets of first erasure coding data for the first data, wherein x+y=M; 
 storing a stripe of the first data in each of M-x subdivisions in the first volume; and 
 storing a set of first erasure coding data in each of the remaining subdivisions in the first volume; and 
 
 with the second set of processor threads:
 separating the second data into x stripes; 
 generating y sets of second erasure coding data for the second data; 
 storing a stripe of the second data in each of M-x subdivisions in the second volume; and 
 storing a set of second erasure coding data in each of the remaining subdivisions in the second volume. 
 
 
     
     
       13. A storage array system, comprising:
 a storage array comprising a plurality of storage devices each divided into at least N subdivisions such that the storage array comprises a plurality of volumes, wherein a volume comprises a set of subdivisions including a subdivision in each of M different storage devices in the plurality of storage devices; 
 a storage array controller comprising:
 memory management circuitry configured to:
 receive first data and second data for storing in the storage array; and 
 select a first volume for storing the first data; and 
 select a second volume for storing the second data, wherein the second volume comprises a different set of subdivisions than the first volume; and 
 
 at least one processor configured to:
 use a first set of processor threads to process the first data and store the first data in the first volume; and 
 concurrent with the processing and storing of the first data, use a second set of processor threads to process the second data and store the second data in the second volume. 
 
 
 
     
     
       14. The storage array system of  claim 13 , further comprising dividing circuitry configured to subdivision the storage devices into at least N namespaces, wherein each namespace corresponds to a subdivision. 
     
     
       15. The storage array system of  claim 13 , wherein the first set of processor threads and the second set of processor threads are executed by a same processor core. 
     
     
       16. The storage array system of  claim 13 , wherein the first set of processor threads and the second set of processor threads are hyper-threads. 
     
     
       17. The storage array system of  claim 13 , wherein the at least one processor is configured to:
 use the first set of processor threads to:
 separate the first data into x stripes; 
 generate y sets of first erasure coding data for the first data, wherein x+y=M; 
 store a stripe of the first data in each of M-x subdivisions in the first volume; and 
 store a set of first erasure coding data in each of the remaining subdivisions in the first volume; and 
 
 use the second set of processor threads to:
 separate the second data into x stripes; 
 generate y sets of second erasure coding data for the second data; 
 store a stripe of the second data in each of M-x subdivisions in the second volume; and 
 store a set of second erasure coding data in each of the remaining subdivisions in the second volume. 
 
 
     
     
       18. The storage array system of  claim 13 , further comprising thread selection circuitry configured to:
 receive a request to access the first data; and 
 select a set of processor threads to access the first volume based on a present operating condition of the storage array system. 
 
     
     
       19. The storage array system of  claim 13 , further comprising thread selection circuitry configured to:
 statically assign the first set of processor threads to the first volume; 
 receive a request to access the first data; and 
 select the first set of processor threads to access the first volume. 
 
     
     
       20. The storage array system of  claim 13 , wherein the at least one processor is configured to:
 use the first set of processor threads to process the first data to generate first erasure coding data store the first erasure coding data in the first volume; and 
 use the second set of processor threads to process the second data to generate second erasure coding data and store the second erasure coding data in the second volume.