Method for improving the execution time of a computer application

Abstract

A method for improving the execution time of a computer application comprises at least one cycle includes: a step of determining the type of memory access time sequence occurring during execution of the computer application; a step of preloading data, from a file system to a cache memory system, according to the determined type of memory access time sequence. The determination step is carried out by a learning model having been previously configured using a database of certain predetermined types of memory access time sequences.

The invention claimed is: 
     
       1. A method for improving the execution time of a computer application, comprising at least one cycle comprising:
 a step of determining a type of memory access time sequence occurring during execution of said computer application; and 
 a step of preloading data, from a file system to a cache memory system, according to the determined type of memory access time sequence, 
 wherein said step of determining is carried out by a learning model having been previously configured using a database containing certain predetermined types of memory access time sequences, and extracting from said database data representative of the types of memory access time sequences contained in the database, the data representative of the types of memory access time sequences being grouped into multidimensional vectors injected in the learning model during configuration of said learning model. 
 
     
     
       2. The method according to  claim 1 , wherein:
 said cycle is repeated continuously and in real time. 
 
     
     
       3. The method according to  claim 1 , wherein:
 said step of preloading data respectively associates predetermined types of memory access time sequences with predetermined data preloading types. 
 
     
     
       4. The method according to  claim 1 , wherein the memory access time sequence comprises at least 30 memory access operations which follow one another in time. 
     
     
       5. The method according to  claim 4 , wherein:
 the memory access time sequence is in the form of a temporally sliding window and comprises a fixed number of operations. 
 
     
     
       6. The method according to  claim 1 , wherein:
 the cycle comprises, after said step of preloading data, a step of using said preloaded data in the cache memory system. 
 
     
     
       7. The method according to  claim 1 , wherein:
 said learning model has previously been configured only once, using a database of certain predetermined types of memory access time sequences, said learning model being reconfigurable in the event that at least one new predetermined type of memory access time sequence is added to said database. 
 
     
     
       8. The method according to  claim 1 , wherein:
 the type of memory access time sequence is defined by a variation over time of two characteristics: the size of data blocks that are read and/or written, and a position of the data blocks in a memory area where the data blocks are read and/or written. 
 
     
     
       9. The method according to  claim 1 , wherein:
 said learning model is based on the use of a “k-means” type of algorithm. 
 
     
     
       10. The method according to  claim 9 , wherein:
 a number of classes of said algorithm is strictly greater than a number of predetermined data preloading types. 
 
     
     
       11. The method according to  claim 9 , wherein:
 a number of classes of said algorithm is between 2 and 10. 
 
     
     
       12. The method according to  claim 1 , wherein the cycle successively comprises, prior to said step of determining:
 a step of extracting data properties representative of the type of memory access time sequence, followed by a step of grouping the extracted properties into multidimensional vectors, 
 said step of extracting data properties being preceded by a preprocessing step which performs a normalization of said representative data, 
 said step of grouping being followed by a step of projection by principal component analysis, reducing a number of dimensions of said vectors. 
 
     
     
       13. The method according to  claim 1 , wherein:
 said computer application runs in at least hundreds of processes of a set of compute nodes of a same network, and 
 said application has access to hundreds of files from a same process. 
 
     
     
       14. A method for improving the execution time of a computer application, comprising at least one cycle comprising:
 a step of determining a type of memory access time sequence occurring during execution of said computer application, 
 a step of preloading data, from a file system to a cache memory system, according to the determined type of memory access time sequence, 
 said determination step carried out by a learning model having been previously configured using a database of predetermined types of memory access time sequences, 
 wherein the predetermined types of memory access time sequences of said determination step comprises four different types of memory access time sequence:
 a sequential access type, where data blocks are consecutively read and/or written in a memory area, 
 a multi-sequential access type with a regular offset between the sequences, where data blocks are read and/or written from plural different locations in a memory area, switching regularly from one location to another, 
 a random access type, and 
 a complex access type, where the sequence is formed of regular or quasi-regular subsequences which are repeated but in a disordered manner and/or where the sequence is regular or quasi-regular and is formed of subsequences which are repeated but in a disordered manner, 
 
 and wherein the preloading step is performed for each of the types of memory access time sequence, except for the random access type for which no data are preloaded in the preloading step. 
 
     
     
       15. The method for improving the execution time of a computer application according to  claim 1 , wherein:
 the determination step comprises four types of memory access time sequence, which are:
 the sequential access type, where data blocks are consecutively read and/or written in a memory area, 
 the multi-sequential access type with a regular offset between the sequences, where data blocks are read and/or written from several different locations in a memory area, switching regularly from one location to another, 
 the random access type, 
 the complex access type, where the sequence is formed of regular or quasi-regular subsequences which are repeated but in a disordered manner and/or where the sequence is regular or quasi-regular and is formed of subsequences which are repeated but in a disordered manner.