Solid-state imaging device and imaging system

Abstract

A solid-state imaging device includes: a first semiconductor substrate including a photoelectric conversion element; and a second semiconductor substrate including at least a part of a peripheral circuit arranged in a main face of the second semiconductor substrate, the peripheral circuit generating a signal based on the charge of the photoelectric conversion element, a main face of the first semiconductor substrate and the main face of the second semiconductor substrate being opposed to each other with sandwiching a wiring structure therebetween; a pad to be connected to an external terminal; and a protection circuit electrically connected to the pad and to the peripheral circuit, wherein the protection circuit is arranged in the main face of the second semiconductor substrate.

The invention claimed is: 
     
       1. A device comprising:
 a first semiconductor substrate which has a first part and a second part, the second part being arranged between the first part and an end face of the first semiconductor substrate, a plurality of pixels being arranged not in the second part but in the first part; and 
 a second semiconductor substrate which has a third part and a fourth part, the fourth part being arranged between the third part and an end face of the second semiconductor substrate; and 
 a wiring structure which is arranged between the first semiconductor substrate and the second semiconductor substrate, 
 wherein the first part and the third part overlap each other, 
 the second part and the fourth part overlap each other, 
 the third part is thicker than the first part, 
 the first part is, between the first part and the third part, electrically connected to the third part via the wiring structure, 
 an external terminal is, through the second part or the fourth part, electrically connected to a circuit of the second semiconductor substrate via the wiring structure, 
 the third part includes a well provided with transistors, and 
 the fourth part includes another well provided with at least one transistor. 
 
     
     
       2. The device according to  claim 1 , wherein the external terminal is electrically connected to the circuit of the second semiconductor substrate through the second part, the second part is provided with an opening where the external terminal is arranged, and the opening is arranged between the first part and the end face of the first semiconductor substrate. 
     
     
       3. The device according to  claim 2 , wherein the external terminal is a bonding wire. 
     
     
       4. The device according to  claim 1 , wherein the circuit includes an input terminal (IN) and an output terminal (OUT), the input terminal and the output terminal being arranged in the fourth part not to overlap with the plurality of pixels. 
     
     
       5. The device according to  claim 4 , wherein the circuit is connected to another circuit of the second semiconductor substrate, and the second semiconductor substrate is provided with a scanning circuit. 
     
     
       6. The device according to  claim 1 , wherein the circuit is a protection circuit. 
     
     
       7. The device according to  claim 1 , wherein the circuit includes diodes. 
     
     
       8. The device according to  claim 1 , wherein the fourth part is provided with an n-type transistor and a p-type transistor. 
     
     
       9. The device according to  claim 1 , wherein the wiring structure includes at least two wiring layers whose main component is copper, and includes at least one wiring layer whose main component is aluminum. 
     
     
       10. The device according to  claim 9 , further comprising a plurality of micro lenses arranged above the first part, wherein one wiring layer is arranged between the first semiconductor substrate and the second semiconductor substrate. 
     
     
       11. The device according to  claim 1 , wherein the wiring structure includes at least two wiring layer whose main component is copper, and a number of layers between the two wiring layer and the first semiconductor substrate is less than a number of layers between the two wiring layer and the second semiconductor substrate. 
     
     
       12. The device according to  claim 1 , wherein the external terminal is connected to a pad which has a surface in contact with the external terminal, and a distance between the surface of the pad and the second semiconductor substrate is smaller than a distance between the first semiconductor substrate and the second semiconductor substrate. 
     
     
       13. The device according to  claim 1 , wherein the first part is electrically connected to the third part via a connection portion in which a first metal portion and a second metal portion are directly bonded, and wherein a main component of the first metal portion and the second metal portion is copper. 
     
     
       14. The device according to  claim 13 , wherein the first part is provided with a first transistor, and the third part is provided with a second transistor electrically connected to the first transistor via the connection portion. 
     
     
       15. The device according to  claim 1 , wherein the fourth part of the second semiconductor substrate is provided with a shallow trench isolation (STI) structure. 
     
     
       16. The device according to  claim 1 , wherein the second part is provided with a circuit element. 
     
     
       17. The device according to  claim 1 , wherein the second semiconductor substrate is provided with a readout circuit for performing an analog-digital conversion. 
     
     
       18. The device according to  claim 1 , wherein the second semiconductor substrate is provided with a control circuit for supplying a control signal to a transistor of the pixel. 
     
     
       19. The device according to  claim 1 , wherein the external terminal is electrically connected to the circuit of the second semiconductor substrate through the fourth part, wherein the fourth part is provided with an through-type electrode which is connected to a wiring included in the wiring structure. 
     
     
       20. An system comprising:
 the device according to  claim 1 ; and 
 a processor configured to process signals output from the device. 
 
     
     
       21. The device according to  claim 1 ,
 wherein a conductivity type of the well is a first conductivity type, 
 wherein a conductivity type of the other well is a second conductivity type. 
 
     
     
       22. The device according to  claim 21 ,
 wherein each of the plurality of pixels includes a photoelectric conversion element having a semiconductor region configured to accumulate charge, and 
 a conductivity type of the semiconductor region is different from the conductivity type of the well. 
 
     
     
       23. A device comprising:
 a first semiconductor substrate which has a first part and a second part, the second part being arranged between the first part and an end face of the first semiconductor substrate, a plurality of pixels being arranged not in the second part but in the first part; and 
 a second semiconductor substrate which has a third part and a fourth part, the fourth part being arranged between the third part and an end face of the second semiconductor substrate; and 
 a wiring structure which is arranged between the first semiconductor substrate and the second semiconductor substrate, the wiring structure including a plurality of insulating films which are continuously layered from the first semiconductor substrate to the second semiconductor substrate, 
 wherein the first part and the third part overlap each other, 
 the second part and the fourth part overlap each other, 
 the first part is, between the first part and the third part, electrically connected to the third part via the wiring structure, 
 an external terminal is, through the second part or the fourth part, electrically connected to a circuit of the second semiconductor substrate via the wiring structure, 
 the third part includes a well provided with transistors, and 
 the fourth part includes another well provided with at least one transistor. 
 
     
     
       24. The device according to  claim 23 , wherein the external terminal is electrically connected to the circuit of the second semiconductor substrate through the second part, the second part is provided with an opening where the external terminal is arranged, and the opening is arranged between the first part and the end face of the first semiconductor substrate. 
     
     
       25. The device according to  claim 24 , wherein the external terminal is a bonding wire. 
     
     
       26. The device according to  claim 23 , wherein the wiring structure includes at least two wiring layers whose main component is copper, and includes at least one wiring layer whose main component is aluminum. 
     
     
       27. The device according to  claim 23 , wherein the wiring structure includes at least two wiring layer whose main component is copper, and a number of layers between the two wiring layer and the first semiconductor substrate is less than a number of layers between the two wiring layer and the second semiconductor substrate. 
     
     
       28. The device according to  claim 23 , wherein the external terminal is connected to a pad which has an exposed surface, and a distance between the exposed surface of the pad and the second semiconductor substrate is smaller than a distance between the first semiconductor substrate and the second semiconductor substrate. 
     
     
       29. The device according to  claim 23 , wherein the first part is electrically connected to the third part via a connection portion in which a first metal portion and a second metal portion are directly bonded. 
     
     
       30. The device according to  claim 23 , wherein the fourth part of the second semiconductor substrate is provided with a shallow trench isolation (STI) structure. 
     
     
       31. The device according to  claim 23 , wherein the external terminal is electrically connected to the circuit of the second semiconductor substrate through the fourth part, wherein the fourth part is provided with an through-type electrode which is connected to a wiring included in the wiring structure. 
     
     
       32. An system comprising:
 the device according to  claim 23 ; and 
 a processor configured to process signals output from the device. 
 
     
     
       33. The device according to  claim 23 ,
 wherein a conductivity type of the well is a first conductivity type, 
 wherein a conductivity type of the other well is a second conductivity type. 
 
     
     
       34. The device according to  claim 33 ,
 wherein each of the plurality of pixels includes a photoelectric conversion element having a semiconductor region configured to accumulate charge, and 
 a conductivity type of the semiconductor region is different from the conductivity type of the well.