Multi-level cell programming using optimized multiphase mapping with balanced gray code

Abstract

Disclosed are systems and methods for providing programming of multi-level memory cells using an optimized multiphase mapping with a balanced Gray code. A method includes programming, in a first phase, a first portion of data into memory cells in a first-level cell mode. The method may also include reading, from the memory cells, the programmed first portion of the data. The method may also include programming, in a second phase, a second portion of the data into the memory cells in a second-level cell mode, wherein programming the second phase is based on applying, to the read first portion of the data, a mapping from the first-level cell mode to the second-level cell mode. The mapping may be selected based on minimizing an average voltage change of the memory cells from the first to second phase while maintaining a balanced Gray code.

What is claimed is: 
     
       1. A data storage system, comprising:
 memory cells; and 
 one or more controllers configured to cause:
 writing, in a first phase, a first data portion into the memory cells in a first-level cell mode; and 
 writing, in a second phase, a second data portion into the memory cells in a second-level cell mode, based on a mapping between the first-level cell mode and the second-level cell mode, 
 wherein: 
 a difference between transition counts of any two pages of memory pages in the second-level cell mode does not exceed a transition count difference, 
 a sum of the transition counts for the memory pages in the second-level cell mode does not exceed a maximum number of programming levels in the second-level cell mode, 
 a number of transition counts for each page of multiple pages associated with the first phase is different from a number of transition counts for a corresponding page of multiple pages associated with the second phase, and 
 the transition count difference is an integer. 
 
 
     
     
       2. The data storage system of  claim 1 ,
 wherein for the first phase, the one or more controllers are configured to cause writing the first data portion into the memory cells in the first-level cell mode, to provide a first set of significant bits for at least multiple pages of the memory cells, across a first voltage distribution having a first plurality of states, and 
 wherein for the second phase, the one or more controllers are configured to cause writing the first data portion of the memory cells in the second-level cell mode, to provide a second set of significant bits for pages corresponding to the at least multiple pages associated with the first phase, across a second voltage distribution having a second plurality of states. 
 
     
     
       3. The data storage system of  claim 1 , wherein the one or more controllers are configured to cause:
 setting the memory cells into the first-level cell mode, to configure the memory cells in the first-level cell mode to store a first number of bits per cell; 
 setting the memory cells into the second-level cell mode, to configure the memory cells in the second-level cell mode to store a second number of bits per cell, wherein the second number of bits per cell is greater than the first number of bits per cell; 
 programming the memory cells in the first-level cell mode to provide a first voltage distribution having a first maximum voltage; and 
 programming the memory cells in the second-level cell mode to provide a second voltage distribution having a second maximum voltage, 
 wherein the second maximum voltage is greater than the first maximum voltage. 
 
     
     
       4. The data storage system of  claim 1 , wherein a width of a state distribution in the memory cells in the first phase is different from a sum of widths of corresponding state distributions in the memory cells in the second phase according to the mapping. 
     
     
       5. The data storage system of  claim 1 , wherein widths of state distributions of the memory cells in the first phase are not uniform. 
     
     
       6. The data storage system of  claim 5 , wherein the one or more controllers are configured to cause reading, from the memory cells, at least a subset of the written first data portion without using error correction. 
     
     
       7. The data storage system of  claim 1 , wherein the one or more controllers are configured to cause not storing the first data portion in a buffer separate from the memory cells. 
     
     
       8. The data storage system of  claim 1 , wherein the one or more controllers are configured to cause retrieving the mapping as a predetermined value stored in the data storage system. 
     
     
       9. The data storage system of  claim 1 ,
 wherein the mapping is based on minimizing an average voltage change of the memory cells from the first phase to the second phase while maintaining a balanced Gray code for the memory pages in the second-level cell mode, and 
 wherein minimizing the average voltage change comprises:
 determining a total voltage change caused by the second phase with respect to all of the programming levels in the second-level cell mode; 
 dividing the total voltage change by the maximum number of programming levels in the second-level cell mode; and 
 determining that the divided total voltage satisfies a threshold voltage range. 
 
 
     
     
       10. The data storage system of  claim 9 , wherein determining the total voltage change comprises weighting at least one programming level of the programming levels. 
     
     
       11. A method, comprising:
 writing, in a first phase, a first data portion into memory cells in a first-level cell mode; and 
 writing, in a second phase, a second data portion into the memory cells in a second-level cell mode, based on a mapping between the first-level cell mode and the second-level cell mode, 
 wherein: 
 a difference between transition counts of any two pages of memory pages in the second-level cell mode does not exceed a transition count difference, 
 a sum of the transition counts for the memory pages in the second-level cell mode does not exceed a maximum number of programming levels in the second-level cell mode, 
 a number of transition counts for each page of multiple pages associated with the first phase is different from a number of transition counts for a corresponding page of multiple pages associated with the second phase, and 
 the transition count difference is an integer. 
 
     
     
       12. The method of  claim 11 ,
 wherein for the first phase, writing the first data portion into the memory cells in the first-level cell mode causes providing a first set of significant bits for at least multiple pages of the memory cells, across a first voltage distribution having a first plurality of states, and 
 wherein for the second phase, writing the first data portion of the memory cells in the second-level cell mode causes providing a second set of significant bits for pages corresponding to the at least multiple pages associated with the first phase, across a second voltage distribution having a second plurality of states. 
 
     
     
       13. The method of  claim 11 , comprising:
 setting the memory cells into the first-level cell mode, to configure the memory cells in the first-level cell mode to store a first number of bits per cell; 
 setting the memory cells into the second-level cell mode, to configure the memory cells in the second-level cell mode to store a second number of bits per cell, wherein the second number of bits per cell is greater than the first number of bits per cell; 
 programming the memory cells in the first-level cell mode to provide a first voltage distribution having a first maximum voltage; and 
 programming the memory cells in the second-level cell mode to provide a second voltage distribution having a second maximum voltage, 
 wherein the second maximum voltage is greater than the first maximum voltage. 
 
     
     
       14. The method of  claim 11 , wherein a width of a state distribution in the memory cells in the first phase is different from a sum of widths of corresponding state distributions in the memory cells in the second phase according to the mapping. 
     
     
       15. The method of  claim 11 , wherein widths of state distributions of the memory cells in the first phase are not uniform. 
     
     
       16. The method of  claim 11 , comprising retrieving the mapping as a predetermined value stored in a data storage system. 
     
     
       17. The method of  claim 11 ,
 wherein the mapping is based on minimizing an average voltage change of the memory cells from the first phase to the second phase while maintaining a balanced Gray code for the memory pages in the second-level cell mode, and 
 wherein minimizing the average voltage change comprises:
 determining a total voltage change caused by the second phase with respect to all of the programming levels in the second-level cell mode; 
 dividing the total voltage change by the maximum number of programming levels in the second-level cell mode; and 
 determining that the divided total voltage satisfies a threshold voltage range. 
 
 
     
     
       18. An apparatus, comprising:
 means for writing, in a first phase, a first data portion into memory cells in a first-level cell mode; and 
 means for writing, in a second phase, a second data portion into the memory cells in a second-level cell mode, based on a mapping between the first-level cell mode and the second-level cell mode, 
 wherein: 
 a difference between transition counts of any two pages of memory pages in the second-level cell mode does not exceed a transition count difference, 
 a sum of the transition counts for the memory pages in the second-level cell mode does not exceed a maximum number of programming levels in the second-level cell mode, 
 a number of transition counts for each page of multiple pages associated with the first phase is different from a number of transition counts for a corresponding page of multiple pages associated with the second phase, and 
 the transition count difference is an integer. 
 
     
     
       19. The apparatus of  claim 18 , comprising:
 means for setting the memory cells into the first-level cell mode, to configure the memory cells in the first-level cell mode to store a first number of bits per cell; 
 means for setting the memory cells into the second-level cell mode, to configure the memory cells in the second-level cell mode to store a second number of bits per cell, wherein the second number of bits per cell is greater than the first number of bits per cell; 
 means for programming the memory cells in the first-level cell mode to provide a first voltage distribution having a first maximum voltage; and 
 means for programming the memory cells in the second-level cell mode to provide a second voltage distribution having a second maximum voltage, 
 wherein the second maximum voltage is greater than the first maximum voltage. 
 
     
     
       20. The apparatus of  claim 18 ,
 wherein for the first phase, the means for writing the first data portion into the memory cells in the first-level cell mode is configured to cause providing a first set of significant bits for at least multiple pages of the memory cells, across a first voltage distribution having a first plurality of states, and 
 wherein for the second phase, means for writing the first data portion of the memory cells in the second-level cell mode is configured to cause providing a second set of significant bits for pages corresponding to the at least multiple pages associated with the first phase, across a second voltage distribution having a second plurality of states.