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US11111135B2ActiveUtilityPatentIndex 53

Methods and devices for microelectromechanical pressure sensors

Assignee: MY01 IP HOLDINGS INCPriority: Jul 2, 2014Filed: Jul 2, 2015Granted: Sep 7, 2021
Est. expiryJul 2, 2034(~8 yrs left)· nominal 20-yr term from priority
Inventors:CHODAVARAPU VAMSYMERDASSI ADELALLAN CHARLES
H03H 9/2436H03H 9/2452G01L 9/0073H03H 9/2463H03H 9/2431G01L 9/0042H03H 3/0072G01L 9/12B81C 1/00182H03H 2009/2442H03H 9/2478H03H 9/2473H03H 9/2405H03H 9/1057B81C 1/00269H03H 3/0073H03H 9/0561B81B 7/007B81C 1/00301H03H 9/2426B81B 2203/0307
53
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Cited by
32
References
17
Claims

Abstract

MEMS based sensors, particularly capacitive sensors, potentially can address critical considerations for users including accuracy, repeatability, long-term stability, ease of calibration, resistance to chemical and physical contaminants, size, packaging, and cost effectiveness. Accordingly, it would be beneficial to exploit MEMS processes that allow for manufacturability and integration of resonator elements into cavities within the MEMS sensor that are at low pressure allowing high quality factor resonators and absolute pressure sensors to be implemented. Embodiments of the invention provide capacitive sensors and MEMS elements that can be implemented directly above silicon CMOS electronics.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
       1. A method for post-fabrication of a MEMS device, the method comprising:
 providing the MEMS device comprising (i) a handling layer, (ii) a top layer, and (iii) a device layer located between the handling layer and the top layer, wherein the handling layer comprises a first trench on a top face of the handling layer adjacent to the device layer, wherein the top layer comprises a second trench on a bottom face of the top layer adjacent to the device layer, the second trench facing the first trench, wherein a first portion of the top layer is electrically insulated from a second portion of the top layer, wherein the first portion of the top layer extends to the second trench, wherein the device layer comprises a section of silicon positioned between the first trench and the second trench; 
 etching a back face of the handling layer until reaching the first trench, thereby forming an opening extending through the handling layer; and 
 etching the section of silicon of the device layer through the opening in the handling layer, thereby thinning the section of silicon of the device layer to form a flexible membrane that is (i) positioned between the opening and the second trench and (ii) capacitively coupled with the first portion of the top layer. 
 
     
     
       2. The method of  claim 1 , wherein etching the section of silicon of the device layer comprises dry etching the section of silicon of the device layer or wet etching the section of silicon of the device layer. 
     
     
       3. The method of  claim 1 , wherein etching the back face of the handling layer comprises wet etching the back face of the handling layer or dry etching the back face of the handling layer. 
     
     
       4. The method of  claim 1 , wherein the second trench is at a vacuum pressure. 
     
     
       5. The method of  claim 2 , wherein the MEMS device further comprises an insulating layer deposited on the top face of the handling layer adjacent to the device layer, and wherein forming the opening further comprises etching through the insulating layer. 
     
     
       6. The method of  claim 1 , further comprising securing a CMOS electronics wafer to a top face of the top layer opposite the bottom face of the top layer. 
     
     
       7. The method of  claim 1 , wherein thinning the section of silicon of the device layer to form the flexible membrane comprises (i) etching a central portion of the section of silicon of the device layer to a first thickness and (ii) etching an outer portion of the section of silicon of the device layer to a second thickness that is thinner than the first thickness. 
     
     
       8. The method of  claim 1 , wherein etching the section of silicon of the device layer through the opening in the handling layer comprises deep reactive-ion etching the section of silicon of the device layer. 
     
     
       9. The method of  claim 1 , wherein providing the MEMS device comprises (i) forming the first trench on the top face of the handling layer and (ii) bonding the device layer to the handling layer. 
     
     
       10. The method of  claim 9 , wherein providing the MEMS device further comprises (i) forming the second trench on the bottom face of the top layer and (ii) bonding the top layer to the device layer. 
     
     
       11. The method of  claim 10 , wherein the top layer is bonded to the device layer while under a vacuum pressure. 
     
     
       12. The method of  claim 10 , wherein the device layer comprises a first plurality of fingers protruding toward the top layer into the second trench, wherein the top layer comprises a second plurality of fingers protruding toward the device layer into the second trench, and wherein bonding the top layer to the device layer comprises bonding the top layer to the device layer such that the first plurality of fingers and the second plurality of fingers are interdigitated. 
     
     
       13. The method of  claim 10 , wherein bonding the top layer to the device layer comprises bonding the second portion of the top layer to the device layer. 
     
     
       14. The method of  claim 9 , wherein the top layer further comprises an annulus with finite thickness that insulates the first portion of the top layer from the second portion of the top layer. 
     
     
       15. The method of  claim 14 , wherein the first portion of the top layer is electrically connected to a first electrode of the MEMS device, wherein the second portion of the top layer is electrically connected to a second electrode of the MEMS device. 
     
     
       16. The method of  claim 14 , further comprising forming a first electrical contact on the first portion of the top layer and a second electrical contact on the second portion of the top layer. 
     
     
       17. The method of  claim 16 , further comprising bonding the first electrical contact and the second electrical contact to a CMOS circuit.

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