Filter apparatus and control method

Abstract

A system includes an analog-to-digital converter configured to convert an analog signal generated by a digital sensor into a digital signal, and a testing apparatus configured to be enabled after the analog-to-digital converter operates in a testing mode, wherein the testing apparatus comprises a filter configured to receive the digital signal from the analog-to-digital converter, and apply a filtering process to the digital signal, a control circuit configured to terminate the filtering process after an output of the control circuit reaches a predetermined reference value, and a result register configured to receive a result generated by the filter after the control circuit terminates the filtering process.

What is claimed is: 
     
       1. A system comprising:
 an analog-to-digital converter configured to convert an analog signal generated by a digital sensor into a digital signal; and 
 a testing apparatus configured to be enabled after the analog-to-digital converter operates in a testing mode, wherein the testing apparatus comprises:
 a filter configured to receive the digital signal from the analog-to-digital converter, and apply a filtering process to the digital signal, wherein as a result of applying the filtering process, the digital signal having a first sample rate is converted into a result having a second sample rate lower than the first sample rate, and wherein in the filtering process, the filter keeps accumulating values of the digital signal until the number of clock cycles reaches a predetermined reference value; 
 a control circuit configured to terminate the filtering process after an output of the control circuit reaches the predetermined reference value; and 
 a result register configured to receive a result generated by the filter after the control circuit terminates the filtering process. 
 
 
     
     
       2. The system of  claim 1 , wherein:
 the analog-to-digital converter is a delta-sigma analog-to-digital converter. 
 
     
     
       3. The system of  claim 1 , further comprising:
 an intermediate stage configured to control data transferring form the result register to an output register. 
 
     
     
       4. The system of  claim 3 , wherein:
 the digital sensor is a digital silicon microphone; 
 the filter is an integrator; 
 the control circuit is a counter; and 
 the intermediate stage is a synchronization stage, and wherein the integrator, the counter, the result register, the synchronization stage and the output register form a testing circuit configured to perform a sensitivity measurement on the digital silicon microphone. 
 
     
     
       5. The system of  claim 4 , wherein:
 the testing circuit comprises a single integrator configured as a filter apparatus for converting the output signal of the analog-to-digital converter having the first sample rate into an output signal of the testing circuit having the second sample rate. 
 
     
     
       6. The system of  claim 5 , wherein:
 a ratio of the first sample rate of the output signal of the analog-to-digital converter to the second sample rate of the output signal of the testing circuit is equal to the predetermined reference value. 
 
     
     
       7. The system of  claim 1 , wherein:
 the testing apparatus and the analog-to-digital converter are disposed on a single semiconductor substrate. 
 
     
     
       8. The system of  claim 1 , wherein:
 the predetermined reference value is determined based on an oversampling rate of the analog-to-digital converter. 
 
     
     
       9. A method comprising:
 configuring an analog-to-digital converter to operate in a testing mode; 
 configuring a filter to receive a stream of bits generated by the analog-to-digital converter, and accumulate values of the stream of bits until the number of clock cycles reaches a predetermined reference value, wherein an output signal of the filter is increased by 1 in response to a digital bit of 1 from the stream of bits, and the output signal of the filter is decreased by 1 in response to a digital bit of 0 from the stream of bits; and 
 transferring the output signal of the filter into a result register. 
 
     
     
       10. The method of  claim 9 , further comprising:
 prior to the step of configuring the filter to receive the stream of bits generated by the analog-to-digital converter, and accumulate the values of the stream of bits, resetting the filter. 
 
     
     
       11. The method of  claim 9 , further comprising:
 resetting a counter; 
 in each clock cycle, increasing the counter by 1; and 
 transferring the output signal of the filter into the result register after the counter reaches the predetermined reference value. 
 
     
     
       12. The method of  claim 9 , further comprising:
 transferring the output signal into the result register to an output register in response to a synchronization signal. 
 
     
     
       13. The method of  claim 9 , wherein:
 the analog-to-digital converter is a delta-sigma analog-to-digital converter having a first sample rate; and 
 a ratio of the first sample rate of the delta-sigma analog-to-digital converter to a second sample rate of the output signal of the filter is equal to the predetermined reference value. 
 
     
     
       14. The method of  claim 9 , further comprising:
 providing a testing signal to the analog-to-digital converter; 
 converting the testing signal into a first digital signal having a first sample rate; 
 decimating the first digital signal by a factor equal to the predetermined reference value using the filter; and 
 determining a sensitivity of the analog-to-digital converter based on a result from the step of decimating the first digital signal by the factor equal to the predetermined reference value using the filter. 
 
     
     
       15. A system comprising:
 a delta-sigma analog-to-digital converter having inputs coupled to a digital sensor; 
 a digital logic circuit having an input connected to the delta-sigma analog-to-digital converter, the digital logic circuit being configured to process an output signal of the delta-sigma analog-to-digital converter during a normal operation mode; and 
 a testing circuit comprising a filter configured to receive a first stream of digital bits from an output of the delta-sigma analog-to-digital converter, and apply an integration process to the first stream of digital bits to generate a second stream of digital bits, wherein a sample rate of the second stream of digital bits is a fraction of a sample rate of the first stream of digital bits, and wherein in the integration process, the filter keeps accumulating values of the first stream of digital bits until the number of clock cycles reaches a predetermined reference value. 
 
     
     
       16. The system of  claim 15 , wherein the testing circuit comprises:
 the filter configured to receive the first stream of digital bits; 
 a control circuit configured to terminate the integration process after an output of the control circuit reaches the predetermined reference value; 
 a result register configured to receive a result generated by the filter after the control circuit terminates the integration process; 
 an output register configured to receive the result from the result register; and 
 an intermediate stage configured to control data transferring form the result register to the output register. 
 
     
     
       17. The system of  claim 16 , wherein the control circuit is a counter, and wherein:
 the counter is configured as a sample rate converter to reduce the sample rate of the first stream of digital bits. 
 
     
     
       18. The system of  claim 15 , wherein:
 a ratio of the sample rate of the first stream of digital bits to the sample rate of the second stream of digital bits is equal to an oversampling rate of the delta-sigma analog-to-digital converter. 
 
     
     
       19. The system of  claim 15 , wherein:
 the delta-sigma analog-to-digital converter, the digital logic circuit and the testing circuit are disposed on a single semiconductor substrate.