Mixed-mode radio frequency front-end interface

Abstract

The described systems, apparatus and methods enable communication between devices that use a single-wire link and devices that use a multi-wire link. One method performed at a master device includes transmitting a sequence start condition over a data wire of a serial bus, the sequence start condition indicating whether clock pulses are to be provided in a clock signal on a clock wire of the serial bus concurrently with a transaction initiated by the sequence start condition, transmitting a first datagram over the serial bus when the sequence start condition indicates that the clock pulses are to be concurrently provided in the clock signal, and transmitting a second datagram over the serial bus when the sequence start condition indicates that no clock pulses are to be concurrently provided in the clock signal. The second datagram may be transmitted in a data signal with embedded timing information.

What is claimed is: 
     
       1. A method of data communication, comprising:
 transmitting a sequence start condition over a data wire of a serial bus, the sequence start condition indicating whether clock pulses are to be provided in a clock signal on a clock wire of the serial bus concurrently with a transaction initiated by the sequence start condition; 
 transmitting a first datagram over the serial bus when the sequence start condition indicates that the clock pulses are to be concurrently provided in the clock signal; 
 transmitting a second datagram over the serial bus when the sequence start condition indicates that no clock pulses are to be concurrently provided on the clock wire of the serial bus, wherein the second datagram is transmitted in a data signal with embedded timing information; and 
 suppressing transmission of sequence start conditions that indicate the clock pulses are to be concurrently provided in the clock signal when the serial bus is reserved for one-wire mode of communication. 
 
     
     
       2. The method of  claim 1 , wherein the sequence start condition has a first duration when indicating that the clock pulses are to be concurrently provided in the clock signal and a second duration longer than the first duration when indicating that no clock pulses are to be concurrently provided on the clock wire of the serial bus. 
     
     
       3. The method of  claim 1 , wherein first data is encoded in the data signal using a pulse-width modulation encoder. 
     
     
       4. The method of  claim 3 , wherein second data is encoded in the data signal using a phase modulation encoder. 
     
     
       5. The method of  claim 3 , further comprising:
 transmitting a bit-timing reference over the data wire before transmitting the second datagram. 
 
     
     
       6. The method of  claim 5 , further comprising:
 controlling timing of the sequence start condition using a first clock frequency; and 
 pulse-width modulating the data signal using a second clock frequency. 
 
     
     
       7. The method of  claim 6 , wherein the second clock frequency is identified by the bit-timing reference. 
     
     
       8. The method of  claim 1 , wherein transmitting the sequence start condition comprises:
 causing a signaling state of the data wire to transition from a first voltage level to a second voltage level while suppressing transitions on the clock wire when the data wire and the clock wire are determined to be idle, wherein an idle signaling state is defined as the first voltage level or the second voltage level by a configuration register. 
 
     
     
       9. A data communication apparatus, comprising:
 an interface circuit adapted to couple the data communication apparatus to two wires of a serial bus; and 
 a protocol controller configured to:
 transmit a sequence start condition over a data wire of the serial bus, the sequence start condition indicating whether clock pulses are to be provided in a clock signal on a clock wire of the serial bus concurrently with a transaction initiated by the sequence start condition; 
 transmit a first datagram over the serial bus when the sequence start condition indicates that the clock pulses are to be concurrently provided in the clock signal; 
 transmit a second datagram over the serial bus when the sequence start condition indicates that no clock pulses are to be concurrently provided on the clock wire of the serial bus, 
 wherein the second datagram is transmitted in a data signal with embedded timing information; and 
 suppress transmission of sequence start conditions that indicate the clock pulses are to be concurrently provided in the clock signal when the serial bus is reserved for one-wire mode of communication. 
 
 
     
     
       10. The data communication apparatus of  claim 9 , wherein the sequence start condition has a first duration when indicating that the clock pulses are to be concurrently provided in the clock signal and a second duration longer than the first duration when indicating that no clock pulses are to be concurrently provided on the clock wire of the serial bus. 
     
     
       11. The data communication apparatus of  claim 9 , further comprising:
 a pulse-width modulation encoder configured to encode first data in the data signal. 
 
     
     
       12. The data communication apparatus of  claim 11 , further comprising:
 a phase modulation encoder configured to encode second data in the data signal. 
 
     
     
       13. The data communication apparatus of  claim 11 , wherein the protocol controller is further configured to:
 transmit a bit-timing reference over the data wire before transmitting the second datagram. 
 
     
     
       14. The data communication apparatus of  claim 13 , wherein the protocol controller is further configured to:
 control timing of the sequence start condition using a first clock frequency; and 
 pulse-width modulate the data signal using a second clock frequency. 
 
     
     
       15. The data communication apparatus of  claim 14 , wherein the second clock frequency is identified by the bit-timing reference. 
     
     
       16. The data communication apparatus of  claim 9 , wherein the protocol controller transmits the sequence start condition by:
 causing a signaling state of the data wire to transition from a first voltage level to a second voltage level while suppressing transitions on the clock wire when the data wire and the clock wire are determined to be idle, wherein an idle signaling state is defined as the first voltage level or the second voltage level by a configuration register.