Memory system having plural circuits separately disposed from memories

Abstract

A memory system includes a first substrate including a first signal terminal and a second signal terminal electrically connected to a bus, a first circuit in which a first switching element and a first resistor are connected in series between a first terminal and a second terminal, the first terminal connected to the first signal terminal, a second circuit in which a second switching element and a second resistor are connected in series between a third terminal and a fourth terminal, the third terminal connected to the second signal terminal, a first memory electrically connected to the second terminal, a second memory electrically connected to the fourth terminal, and a controller electrically connected to the bus and configured to control the first and second switching elements.

What is claimed is: 
     
       1. A memory system comprising:
 a first substrate including a first signal terminal and a second signal terminal electrically connected to a bus; 
 a second substrate having first and second surfaces that are opposite to each other, the first surface facing a surface of the first substrate, the second substrate including:
 a first circuit in which a first switching element and a first resistor are connected in series between a first terminal and a second terminal, the first terminal connected to the first signal terminal, and 
 a second circuit in which a second switching element and a second resistor are connected in series between a third terminal and a fourth terminal, the third terminal connected to the second signal terminal; 
 
 a third substrate facing the second surface of the second substrate and including a first memory electrically connected to the second terminal; 
 a fourth substrate facing the second surface of the second substrate and including a second memory electrically connected to the fourth terminal; and 
 a controller electrically connected to the bus and configured to control the first and second switching elements. 
 
     
     
       2. The memory system according to  claim 1 , wherein
 the controller is configured to turn on the first switching element while turning off the second switching element when reading or writing data from or to the first memory. 
 
     
     
       3. The memory system according to  claim 1 , wherein
 the controller is configured to issue a selection signal to select one of the first and second memories for reading or writing operations, and 
 the first and second switching elements are turned on or off according to the selection signal. 
 
     
     
       4. The memory system according to  claim 1 , wherein
 the controller is disposed on the first substrate. 
 
     
     
       5. The memory system according to  claim 1 , wherein
 the first and second circuits are included in a semiconductor integrated circuit. 
 
     
     
       6. The memory system according to  claim 5 , wherein
 the second substrate is an interposer circuit, and 
 the semiconductor integrated circuit is mounted on the interposer circuit with a bump. 
 
     
     
       7. The memory system according to  claim 5 , wherein
 the semiconductor integrated circuit is disposed on one surface of the second substrate. 
 
     
     
       8. The memory system according to  claim 7 , wherein
 the semiconductor integrated circuit is disposed at a center of said one surface of the second substrate. 
 
     
     
       9. The memory system according to  claim 5 , further comprising:
 a fifth substrate between the second substrate and at least one of the first and second memories, wherein 
 the semiconductor integrated circuit is disposed on one surface of the second substrate facing the fifth substrate. 
 
     
     
       10. The memory system according to  claim 1 , wherein
 the second terminal is connected to a command signal terminal or an address signal terminal of the first memory. 
 
     
     
       11. The memory system according to  claim 1 , wherein
 a storage capacity of the first memory is different from a storage capacity of the second memory. 
 
     
     
       12. The memory system according to  claim 11 , wherein
 the first memory has dual die package structure, and 
 the second memory has single die package structure. 
 
     
     
       13. A memory system comprising:
 a first substrate including a first signal terminal and a second signal terminal electrically connected to a bus; 
 a second substrate facing one surface of the first substrate and including:
 a first circuit in which a first switching element and a first resistor are connected in series between a first terminal and a second terminal, the first terminal being connected to the first signal terminal, and 
 a first memory having dual die package structure and electrically connected to the second terminal; 
 
 a third substrate facing the other surface of the first substrate and including:
 a second circuit in which a second switching element and a second resistor are connected in series between a third terminal and a fourth terminal, the third terminal being connected to the second signal terminal, and 
 a second memory having single die package structure and electrically connected to the fourth terminal; and 
 
 a controller electrically connected to the bus and configured to control the first and second switching elements. 
 
     
     
       14. The memory system according to  claim 13 , wherein
 the first and second signal terminals are arranged adjacent to each other across the first substrate. 
 
     
     
       15. The memory system according to  claim 1 , wherein
 each of the first and second memories is a double-data-rate 4 (DDR4) memory. 
 
     
     
       16. The memory system according to  claim 1 , wherein
 each of the first and second memories is a synchronous dynamic random access memory (SDRAM). 
 
     
     
       17. The memory system according to  claim 1 , further comprising:
 a non-volatile semiconductor memory. 
 
     
     
       18. A memory system comprising:
 a first substrate having first and second surfaces that are opposite to each other and including a first signal terminal and a second signal terminal electrically connected to a bus; 
 a second substrate having third and fourth surfaces that are opposite to each other, the third surface facing one of the first and second surfaces of the first substrate, the second substrate including a first circuit in which a first switching element and a first resistor are connected in series between a first terminal and a second terminal, the first terminal connected to the first signal terminal; 
 a third substrate having fifth and sixth surfaces that are opposite to each other, the fifth surface facing one of the first and second surfaces of the first substrate, the third substrate including a second circuit in which a second switching element and a second resistor are connected in series between a third terminal and a fourth terminal, the third terminal connected to the second signal terminal; 
 a fourth substrate facing the fourth surface of the second substrate and including a first memory electrically connected to the second terminal; 
 a fifth substrate facing the sixth surface of the third substrate and including a second memory electrically connected to the fourth terminal; and 
 a controller electrically connected to the bus and configured to control the first and second switching elements. 
 
     
     
       19. The memory system according to  claim 1 , wherein
 the first resistor is connected between the first terminal and the first switching element, and 
 the second resistor is connected between the third terminal and the second switching element. 
 
     
     
       20. The memory system according to  claim 1 , wherein
 the first substrate further includes a selection signal terminal through which a selection signal for selecting a memory is output, and 
 the first circuit includes a fifth terminal connected to the selection signal terminal and a sixth terminal through which the selection signal is output to the first memory.