Semiconductor devices

Abstract

A semiconductor device includes an error check and scrub (ECS) command generation circuit and an ECS control circuit. The ECS command generation circuit is configured to generate an ECS command by controlling a speed of a first counting operation that is performed based on a refresh command or a bank refresh command, according to a temperature and a refresh mode of the semiconductor device, or is configured to generate the ECS command by performing a second counting operation based on a periodic signal. The ECS control circuit is configured to sequentially generate an ECS active command, an ECS read command, an ECS write command, an ECS pre-charge command, and an end signal based on the ECS command. The refresh mode includes a fine granularity refresh (FGR) mode, and the temperature includes a high temperature that is a temperature above a certain temperature.

What is claimed is: 
     
       1. A semiconductor device comprising:
 an error check and scrub (ECS) command generation circuit configured to generate an ECS command by controlling a speed of a first counting operation that is performed based on a refresh command or a bank refresh command, according to a temperature and a refresh mode of the semiconductor device, or configured to generate the ECS command by performing a second counting operation based on a periodic signal; and 
 an ECS control circuit configured to sequentially generate an ECS active command, an ECS read command, an ECS write command, an ECS pre-charge command, and an end signal based on the ECS command, 
 wherein the refresh mode includes a fine granularity refresh (FGR) mode, and the temperature includes a high temperature that is a temperature above a certain temperature. 
 
     
     
       2. The semiconductor device of  claim 1 , wherein a frequency of the refresh command in the FGR mode is set to be ‘2M’ times a frequency of the refresh command in a non-FGR mode,
 wherein the number ‘M’ is a natural number. 
 
     
     
       3. The semiconductor device of  claim 1 , wherein a frequency of the refresh command at the high temperature is set to be ‘2N’ times a frequency of the refresh command at a non-high temperature,
 wherein the number ‘N’ is a natural number. 
 
     
     
       4. The semiconductor device of  claim 1 , wherein the ECS command generation circuit generates the ECS command by performing the first counting operation when the refresh command is generated at a non-high temperature in a non-FGR mode. 
     
     
       5. The semiconductor device of  claim 1 , wherein the ECS command generation circuit generates the ECS command by performing the first counting operation when all bit signals of the refresh command or the bank refresh command are generated ‘2M’ times at a non-high temperature in the FGR mode,
 wherein the number ‘M’ is a natural number. 
 
     
     
       6. The semiconductor device of  claim 1 , wherein the ECS command generation circuit generates the ECS command by performing the first counting operation when the refresh command is generated ‘2N’ times at the high temperature in a non-FGR mode,
 wherein the number ‘N’ is a natural number. 
 
     
     
       7. The semiconductor device of  claim 1 , wherein the ECS command generation circuit generates the ECS command by performing the first counting operation whenever all of bit signals of the refresh command or the bank refresh command are generated ‘2M×2N’ times at the high temperature in the FGR mode,
 wherein the numbers ‘M’ and ‘N’ are natural numbers. 
 
     
     
       8. The semiconductor device of  claim 1 , wherein the ECS command generation circuit includes an FGR command generation circuit that is configured to generate an FGR command when all bit signals of the refresh command or the bank refresh command are generated in the FGR mode. 
     
     
       9. The semiconductor device of  claim 8 , wherein the ECS command generation circuit further includes a pre-count flag generation circuit that is configured to generate a pre-count flag when the refresh command is generated in a non-FGR mode or when the FGR command is generated ‘2M’ times in the FGR mode. 
     
     
       10. The semiconductor device of  claim 9 , wherein the ECS command generation circuit is configured to terminate the generation of the pre-count flag when the ECS command is generated while a refresh operation for each of memory banks is performed. 
     
     
       11. The semiconductor device of  claim 9 , wherein the ECS command generation circuit further includes a count flag generation circuit that is configured to generate a count flag when the pre-count flag is generated at a non-high temperature or when the pre-count flag is generated ‘2N’ times at the high temperature,
 wherein the number ‘N’ is a natural number. 
 
     
     
       12. The semiconductor device of  claim 11 , wherein the ECS command generation circuit further includes:
 an external ECS command generation circuit configured to count the count flag to generate an external ECS command; and 
 an ECS command selection circuit configured to output the external ECS command as the ECS command based on a command selection signal. 
 
     
     
       13. The semiconductor device of  claim 1 , wherein the ECS command generation circuit includes:
 an internal ECS command generation circuit configured to count the periodic signal to generate an internal ECS command; and 
 an ECS command selection circuit configured to output the internal ECS command as the ECS command based on a command selection signal. 
 
     
     
       14. A semiconductor device comprising:
 an error check and scrub (ECS) command generation circuit configured to generate an ECS command by controlling a speed of a counting operation performed based on a refresh command or a bank refresh command, according to a temperature and a refresh mode of the semiconductor device; and 
 an ECS control circuit configured to sequentially generate an ECS active command, an ECS read command, an ECS write command, an ECS pre-charge command, and an end signal based on the ECS command, 
 wherein the refresh mode includes a fine granularity refresh (FGR) mode, and the temperature includes a high temperature over a certain temperature. 
 
     
     
       15. The semiconductor device of  claim 14 , wherein the ECS command generation circuit includes an FGR command generation circuit that is configured to generate an FGR command when all bit signals of the refresh command or the bank refresh command are generated in the FGR mode. 
     
     
       16. The semiconductor device of  claim 15 , wherein the ECS command generation circuit further includes a pre-count flag generation circuit that is configured to generate a pre-count flag when the refresh command is generated in a non-FGR mode or when the FGR command is generated ‘2M’ times in the FGR mode. 
     
     
       17. The semiconductor device of  claim 16 , wherein the ECS command generation circuit is configured to terminate the generation of the pre-count flag when the ECS command is generated while a refresh operation for each of memory banks is performed. 
     
     
       18. The semiconductor device of  claim 16 , wherein the ECS command generation circuit further includes a count flag generation circuit that is configured to generate a count flag when the pre-count flag is generated at a non-high temperature or when the pre-count flag is generated ‘2N’ times at the high temperature,
 wherein the number ‘N’ is a natural number. 
 
     
     
       19. The semiconductor device of  claim 18 , wherein the ECS command generation circuit further includes:
 an external ECS command generation circuit configured to count the count flag to generate an external ECS command; and 
 an ECS command selection circuit configured to output the external ECS command as the ECS command based on a command selection signal. 
 
     
     
       20. A semiconductor device comprising:
 a fine granularity refresh (FGR) command generation circuit configured to generate an FGR command when all bit signals of the refresh command or the bank refresh command are generated in an FGR mode; 
 a pre-count flag generation circuit configured to generate a pre-count flag when the refresh command is generated in a non-FGR mode or when the FGR command is generated ‘2M’ times in the FGR mode; 
 a count flag generation circuit configured to generate a count flag when the pre-count flag is generated at a low temperature, the low temperature being below a certain temperature, or when the pre-count flag is generated ‘2N’ times at a high temperature, the high temperature being above the certain temperature; 
 an external ECS command generation circuit configured to count the count flag to generate an external ECS command; and 
 an ECS command selection circuit configured to output the external ECS command as an ECS command for controlling an ECS operation based on a command selection signal, 
 wherein the numbers ‘M’ and ‘N’ are natural numbers. 
 
     
     
       21. A semiconductor device comprising:
 an error check and scrub (ECS) command generation circuit configured to generate an ECS command by performing a counting operation based on a periodic signal; and 
 an ECS control circuit configured to sequentially generate an ECS active command, an ECS read command, an ECS write command, an ECS pre-charge command, and an end signal based on the ECS command, 
 wherein the ECS command generation circuit includes an internal ECS command generation circuit configured to count the periodic signal to generate an internal ECS command, and an ECS command selection circuit configured to output the internal ECS command as the ECS command based on a command selection signal.