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US11145540B2ActiveUtilityPatentIndex 62

Semiconductor structure having air gap dielectric and the method of preparing the same

Assignee: NANYA TECHNOLOGY CORPPriority: Aug 8, 2019Filed: Aug 8, 2019Granted: Oct 12, 2021
Est. expiryAug 8, 2039(~13.1 yrs left)· nominal 20-yr term from priority
Inventors:LAI CHUN-CHI
H10W 20/0633H10W 20/056H10W 20/48H10W 20/42H10W 20/072H10W 20/063H10W 20/077H10W 20/46H10W 20/435H01L 23/5226H01L 21/76877H01L 21/7682H01L 23/5329
62
PatentIndex Score
0
Cited by
33
References
13
Claims

Abstract

The present disclosure provides a semiconductor structure and a method for preparing the semiconductor structure. The semiconductor structure includes a base layer, a plurality of conductive lines, a plurality of dielectric pillars, and a sealing layer having a plurality of sealing caps. The conductive lines are disposed on the base layer. The dielectric pillars are disposed on the base layer and separated from the conductive layer. The sealing caps are disposed between the conductive lines and the dielectric pillars, wherein the sealing caps are in contact with the conductive lines and the dielectric pillars, and separated from the base layer.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
       1. A method of preparing a semiconductor structure, comprising the steps of:
 providing a base layer; 
 forming a plurality of conductive lines on the base layer; 
 after forming the plurality of conductive lines, forming a plurality of spacers on the base layer and the conductive lines, wherein each of the conductive lines are flanked by the spacers, wherein a top width of each of the spacers is less than a bottom width of each of the spacers; 
 forming a plurality of dielectric pillars on the base layer, between the spacers of adjacent two of the plurality of conductive lines, wherein the width of each of the plurality of dielectric pillars gradually increases as they are away from the base layer, and each of the plurality of dielectric pillars has rounding corners, wherein top widths of adjacent two of the plurality of dielectric pillars are different; 
 removing the spacers; and 
 forming a plurality of sealing caps between the conductive lines and the dielectric pillars, wherein the sealing caps are in contact with the conductive lines and the dielectric pillars, and separated from the base layer to form a plurality of air gaps correspondingly positioned between the conductive lines and the dielectric pillars, wherein a top width of each of the air gaps is less than a bottom width of each of the air gaps. 
 
     
     
       2. The method of preparing a semiconductor structure of  claim 1 , further comprising the step of forming a plurality of plugs in the base layer before the step of forming the conductive lines on the base layer, wherein the conductive lines are connected to the plugs. 
     
     
       3. The method of preparing a semiconductor structure of  claim 1 , wherein the step of forming the conductive lines on the base layer comprises
 forming a conductive layer on the base layer; and 
 patterning the conductive layer to form the conductive lines. 
 
     
     
       4. The method of preparing a semiconductor structure of  claim 1 , wherein after forming a plurality of dielectric pillars, a top end of the dielectric pillars is lower than a top end of the conductive lines, and a top portion of the spacer is exposed. 
     
     
       5. The method of preparing a semiconductor structure of  claim 1 , wherein the spacers comprise silicon oxide. 
     
     
       6. The method of preparing a semiconductor structure of  claim 5 , wherein the step of removing the spacers comprises etching the spacers with vapor hydrofluoric acid. 
     
     
       7. The method of preparing a semiconductor structure of  claim 1 , wherein the step of forming the spacers comprises:
 forming a spacer layer on the base layer and the conductive lines; and 
 partly removing of the spacer layer to form the spacers. 
 
     
     
       8. The method of preparing a semiconductor structure of  claim 7 , wherein the step of forming the spacer layer comprises chemical vapor deposition. 
     
     
       9. The method of preparing a semiconductor structure of  claim 7 , wherein partly removing the spacer layer comprises anisotropic etching. 
     
     
       10. The method of preparing a semiconductor structure of  claim 1 , wherein the dielectric pillars comprise hydrogen silsesquioxane, cyclotene, poly(arylene ether) or silicon oxide. 
     
     
       11. The method of preparing a semiconductor structure of  claim 1 , wherein the step of forming the dielectric pillars comprises spin-coating. 
     
     
       12. The method of preparing a semiconductor structure of  claim 11 , wherein the step of forming the dielectric pillars comprises
 filling a dielectric material between the spacers; and 
 drying the dielectric material to form the dielectric pillars. 
 
     
     
       13. The method of preparing a semiconductor structure of  claim 1 , wherein the step of forming the sealing caps comprises spin-coating.

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