Method and circuit for noise shaping SAR analog-to-digital converter

Abstract

An analog-to-digital (A/D) conversion system includes a track-and-hold circuit, a comparison circuit, a control circuit, a digital-to-analog (D/A) conversion circuit, a switched buffer and a loop filter. The track-and-hold circuit is configured to output a first signal based on an input signal or a first timing signal. The comparison circuit is configured to generate a comparison result based on the first signal and a filtered residue signal. The control circuit is coupled to the comparison circuit, and is configured to generate an N-bit logical signal according to N comparison results from the comparison circuit. The D/A circuit is configured to generate a feedback signal based on the N-bit logical signal. The switched buffer is configured to generate a first error signal based on a second timing signal and a second error signal. The loop filter is configured to generate the filtered residue signal based on the first error signal.

What is claimed is: 
     
       1. An analog-to-digital (A/D) conversion system, comprising:
 a track-and-hold circuit configured to output a first signal based on an input signal or a first timing signal; 
 a comparison circuit coupled to the track-and-hold circuit and configured to generate a comparison result based on at least the first signal and a filtered residue signal; 
 a control circuit coupled to the comparison circuit, and configured to generate an N-bit logical signal according to N comparison results from the comparison circuit; 
 a digital-to-analog (D/A) conversion circuit having an output coupled to the comparison circuit, and being configured to generate a feedback signal based on at least the N-bit logical signal; 
 a switched buffer configured to generate a first error signal based on a second timing signal and a second error signal; and 
 a loop filter coupled to the switched buffer and the comparison circuit, and configured to generate the filtered residue signal based on the first error signal. 
 
     
     
       2. The A/D conversion system of  claim 1 , further comprising:
 a coupling circuit coupled to the output of the D/A conversion circuit, the track-and-hold circuit and the switched buffer, and configured to generate the second error signal based on the first signal and the feedback signal. 
 
     
     
       3. The A/D conversion system of  claim 1 , wherein the comparison circuit is further configured to generate the comparison result based on the first signal, the filtered residue signal and the feedback signal. 
     
     
       4. The A/D conversion system of  claim 1 , further comprising:
 an output filter coupled to an output of the control circuit, the output filter configured to receive a third signal from the control circuit, and to output a filtered third signal. 
 
     
     
       5. The A/D conversion system of  claim 1 , wherein the switched buffer is further configured to generate the first error signal by sampling the second error signal in response to the second timing signal being activated during a sampling cycle. 
     
     
       6. The A/D conversion system of  claim 1 , wherein the control circuit is further configured to generate the first timing signal and the second timing signal. 
     
     
       7. The A/D conversion system of  claim 1 , wherein the D/A conversion circuit is further configured to generate the feedback signal based on the N-bit logical signal and a third timing signal, the third timing signal being generated by the control circuit. 
     
     
       8. The A/D conversion system of  claim 1 , wherein the D/A conversion circuit comprises a set of capacitive devices and a set of switches, each capacitive device of the set of capacitive devices being coupled to a corresponding switch of the set of switches, and the set of capacitive devices and the set of switches configured to reconstruct the N-bit logical signal in a form of the feedback signal representing a reconstructed voltage level. 
     
     
       9. The A/D conversion system of  claim 1 , wherein the N-bit logical signal generated by the control circuit is provided to the D/A conversion circuit to generate the feedback signal in a next sampling cycle. 
     
     
       10. An analog-to-digital (A/D) conversion circuit, comprising:
 an N-bit successive approximation register (SAR) analog-to-digital converter (ADC) configured to receive an input voltage, N being a positive integer, and the SAR ADC comprising:
 a capacitor array configured to generate a first signal based on at least the input voltage and a first timing signal; 
 a comparator having a first input coupled to an output of the capacitor array, and configured to generate a comparison result based on the first signal and a filtered residue signal; and 
 a SAR controller coupled to the comparator, and configured to generate an N bit logical signal based on the comparison result after the SAR controller receives N comparison results from the comparator during a sampling cycle, wherein the filtered residue signal is based on the N bit logical signal; 
 
 a switched buffer having an input coupled to the output of the capacitor array, and configured to generate a first error signal based on a second timing signal and a second error signal; and 
 a loop filter coupled to the switched buffer, and configured to generate the filtered residue signal based on the first error signal. 
 
     
     
       11. The A/D conversion circuit of  claim 10 , wherein the capacitor array is further configured to generate
 the first signal based on the input voltage, the first timing signal, a first reference voltage, 
 a second reference voltage, and 
 the second error signal after the comparator generates the N comparison results. 
 
     
     
       12. The A/D conversion circuit of  claim 11 , wherein the capacitor array comprises:
 (N+1) capacitive devices, each capacitive device of the (N+1) capacitive devices having a first end and a second end, an n-th capacitive device of the (N+1) capacitive devices having a capacitance value of 
 
       
         
           
             
               
                 C 
                 
                   2 
                   
                     ( 
                     
                       n 
                       - 
                       1 
                     
                     ) 
                   
                 
               
               , 
             
           
         
       
       where n is a positive integer ranging from 1 to N, and C is a predetermined capacitance value;
 a first node electrically coupled to the first ends of the (N+1) capacitive devices; 
 (N+1) switching devices, each switching device of the (N+1) switching devices coupled to a corresponding second end of each of the (N+1) capacitive devices; and 
 a first switch coupled between the second ends of the (N+1) capacitive devices and a power supply node having a zero reference voltage. 
 
     
     
       13. The A/D conversion circuit of  claim 12 , wherein the first switch is configured to electrically couple the power supply node and the second ends of the (N+1) capacitive devices based on the first timing signal received from the SAR controller. 
     
     
       14. The A/D conversion circuit of  claim 10 , wherein the loop filter has an input and an output, the input of the loop filter being coupled to an output of the switched buffer, and the output of the loop filter being coupled to a second input of the comparator. 
     
     
       15. The A/D conversion circuit of  claim 10 , wherein the loop filter is a high-pass filter comprising:
 at least one integrator, and 
 an amplifier. 
 
     
     
       16. The A/D conversion circuit of  claim 10 , wherein the switched buffer comprises:
 a switch coupled to the capacitor array, and configured to be responsive to the second timing signal received from the SAR controller, and 
 a buffer coupled to the switch, and configured to hold a voltage level of the second error signal from a previous sampling cycle. 
 
     
     
       17. A method of operating an analog-to-digital (A/D) conversion circuit, comprising:
 generating, by a comparator, a comparison result based on a first signal and a filtered residue signal by operating a successive approximation register (SAR) analog-to-digital converter (ADC), the comparator being part of the SAR ADC, and N being a positive integer; 
 generating, by a SAR controller, an N-bit logical signal based on the comparison result after the SAR controller receives N comparison results from the comparator during a sampling cycle, wherein the filtered residue signal is based on the N-bit logical signal; 
 generating, by a capacitor array, the first signal based on the N-bit logical signal, an input signal and a first timing signal, an output of the capacitor array being coupled to a first input of the comparator; 
 generating, by a switched buffer, a sample and hold residue signal based on the first signal and a second timing signal, an input of the switched buffer being coupled to the output of the capacitor array; and 
 generating, by a loop filter, the filtered residue signal based on the sample and hold residue signal of a sampling cycle, the loop filter being coupled to a second input of the comparator. 
 
     
     
       18. The method of  claim 17 , wherein the generating the first signal comprises:
 setting the capacitor array based on the N-bit logical signal, the input signal and the first timing signal, wherein a voltage level of the first signal corresponds to a voltage level of the input signal minus a voltage level corresponding to the N-bit logical signal; and 
 charging the capacitor array based on the input signal and the first timing signal. 
 
     
     
       19. The method of  claim 17 , further comprising:
 generating an output logical signal based on a plurality of N-bit logical signals, each of the plurality of N-bit logical signals corresponds to a different sampling cycle. 
 
     
     
       20. The method of  claim 17 , wherein generating, by the switched buffer, the sample and hold residue signal based on the first signal and the second timing signal comprises:
 causing a switch to close responsive to the second timing signal, the switch being coupled to the capacitor array; and 
 holding, by a buffer, a voltage level of the first signal from a previous sampling cycle, the buffer being coupled to the switch.