Anti-hacking mechanisms for flash memory device

Abstract

Multiple embodiments are disclosed for enhancing security and preventing hacking of a flash memory device. The embodiments prevent malicious actors from hacking a flash memory chip to obtain data that is stored within the chip. The embodiments include the use of fault detection circuits, address scrambling, dummy arrays, password protection, improved manufacturing techniques, and other mechanisms.

What is claimed is: 
     
       1. A flash memory system, comprising:
 an array comprising a plurality of flash memory cells organized into rows and columns; and 
 a logic fault detection circuit comprising:
 a command logic circuit; 
 a replica command logic circuit; and 
 a comparator for comparing an output of the command logic circuit and an output of the replica command logic circuit, wherein the comparator generates a first output value if an output of the command logic circuit and an output of the replica command logic circuit are identical and the comparator generates a second output value if the output of the command logic circuit and the output of the replica command logic circuit are not identical, wherein the first output value enables access to the array and the second output value disables access to the array. 
 
 
     
     
       2. The flash memory system of  claim 1 , wherein the output of the replica command logic circuit indicates an erase, program, read, or test command. 
     
     
       3. The flash memory system of  claim 1 , wherein the command logic circuit and the replica command logic circuit receive input signals from pins of the flash memory system. 
     
     
       4. The flash system of  claim 1 , further comprising address decoding logic. 
     
     
       5. The flash memory system of  claim 1 , wherein the plurality of flash memory cells are split gate flash memory cells. 
     
     
       6. A flash memory system, comprising:
 an array comprising a plurality of flash memory cells organized into rows and columns; and 
 a fault detection circuit for comparing a received erase, program, or read signal against a replica erase, program, or read signal and generating an output based on the comparing, wherein access to the array is enabled if the output is a first value and access to the array is disabled if the output is a second value, wherein the replica erase, program, or read signal is based at least partly on stored configuration data for an erase, program, or read operation. 
 
     
     
       7. The flash memory system of  claim 6 , further comprising address fault detection circuitry. 
     
     
       8. The flash memory system of  claim 6 , wherein the plurality of flash memory cells are split gate flash memory cells. 
     
     
       9. A flash memory system, comprising:
 an array comprising a plurality of flash memory cells organized into rows and columns; 
 an analog mixed signal fault detection circuit; 
 a logic fault detection circuit; and 
 an address fault detection circuit; 
 wherein access to the array is enabled if none of the analog mixed signal fault detection circuit, the logic fault detection circuit, and the address fault detection circuit detects a fault and access to the array is disabled if at least one of the analog mixed signal fault detection circuit, the logic fault detection circuit, or the address fault detection circuit detects a fault. 
 
     
     
       10. The flash memory system of  claim 9 , wherein the plurality of flash memory cells are split gate flash memory cells. 
     
     
       11. A flash memory system, comprising:
 an array comprising a plurality of flash memory cells organized into rows and columns; and 
 power balanced latch sense amplifier circuitry comprising:
 a data read block for sourcing current during a read operation to a selected flash memory cell corresponding to a received address and contained within the plurality of flash memory cells; 
 a reference read block coupled to a holding capacitor; 
 a differential amplifier for comparing current drawn by the data read block and the reference read block during the read operation to generate an output indicative of a value stored in the selected flash memory cell; and 
 a balancing power circuit for maintaining a minimum voltage in the read circuit block in response to any data pattern. 
 
 
     
     
       12. The flash memory system of  claim 11 , wherein the plurality of flash memory cells are split gate flash memory cells.