US11190213B2ActiveUtilityA1
Coding method, wireless device, and chip
Est. expiryJun 16, 2037(~10.9 yrs left)· nominal 20-yr term from priority
H03M 13/13H04L 1/0057H03M 13/635H04L 1/0043H04L 1/00
64
PatentIndex Score
1
Cited by
22
References
20
Claims
Abstract
A coding method, a wireless device, and a chip are described. A coding method may include obtaining, based on a sequence whose length is 2 n′ , a mother code sequence used for coding, where the sequence whose length is 2 n′ includes 2 n′ sequence numbers, a length of the mother code sequence is 2 n , the mother code sequence includes 2 n sequence numbers, the 2 n sequence numbers are some or all of the 2 n′ sequence numbers, n′ is a natural number, and n is a natural number less than or equal to n′. The method may also include coding an input to-be-coded bit by using the mother code sequence. According to this method, a system may store one or more long sequences, and then obtain a required mother code sequence from one of the long sequences according to a coding requirement, thereby reducing storage overheads of the system.
Claims
exact text as granted — not AI-modifiedWhat is claimed is:
1. A coding method, comprising:
obtaining a mother code sequence used for coding from a sequence whose length is 2 n ′ wherein the sequence whose length is 2 n ′ comprises 2 n ′ sequence numbers, a length of the mother code sequence is 2 n ′, the mother code sequence comprises 2 n sequence numbers, the 2 n ′ sequence numbers are a subset of the 2 n ′ sequence numbers, n′ is a positive integer, and n is a positive integer less than or equal to n′; and
coding an input to-be-coded bit by using the mother code sequence.
2. The method according to claim 1 , wherein n=n′−1, and the obtaining, based on the sequence whose length is 2 n′ , the mother code sequence used for coding comprises:
obtaining the mother code sequence based on an even sequence number or an odd sequence number in the sequence whose length is 2 n′ .
3. The method according to claim 1 , wherein the obtaining, based on the sequence whose length is 2 n′ , the mother code sequence used for coding comprises:
obtaining, based on the sequence whose length is 2 n′ , the mother code sequence used for coding, so that any sequence number S′ in the mother code sequence meets the following condition:
S
′
=
S
+
v
2
n
′
-
n
,
wherein
S is a sequence number that meets the following condition in the sequence whose length is 2 n′ :
mod
(
S
+
v
2
n
′
-
n
)
=
0
,
wherein
V is an integer, −2 n′-n <V≤0, and mod is a modulo operator.
4. The method according to claim 1 , wherein the obtaining, based on the sequence whose length is 2 n′ , the mother code sequence used for coding comprises:
extracting 2 n sequence numbers from the 2 n′ sequence numbers in the sequence whose length is 2 n′ , wherein n′−n bits at fixed locations in a binary form of each of the 2 n sequence numbers each are equal to a preset value; and wherein
the mother code sequence is formed based on a sequence represented by using remaining bits obtained after the n′−n bits at the fixed locations are removed from the binary form of each of the 2 n sequence numbers.
5. The method according to claim 1 , wherein an order of the 2 n sequence numbers of the mother code sequence in the mother code sequence is the same as that in the sequence whose length is 2 n′ .
6. The method according to claim 1 , wherein the sequence whose length is 2 n′ is one of a plurality of sequences of different lengths, and before the obtaining, based on the sequence whose length is 2 n′ , the mother code sequence used for coding, the method further comprises:
obtaining the sequence whose length is 2 n′ from the plurality of sequences of different lengths.
7. The method according to claim 1 , wherein the 2 n′ sequence numbers are sequence numbers of 2 n′ channels, and the sequence whose length is 2 n′ is obtained after the sequence numbers of the 2 n′ channels are sorted based on channel reliability.
8. A wireless device, comprising:
a memory configured to store a sequence whose length is 2 n′ , wherein the sequence whose length is 2 n′ comprises 2 n′ sequence numbers, and n′ is a positive integer; and
an encoder configured to:
obtain an input to-be-coded bit, and obtain the sequence whose length is 2 n′ from the memory,
obtain a mother code sequence used for coding from a sequence whose length is 2 n ′, wherein a length of the mother code sequence is 2 n , the mother code sequence comprises 2 n sequence numbers, the 2 n sequence numbers are a subset of the 2 n′ sequence numbers, and n is a positive integer less than or equal to n′, and
code the input to-be-coded bit by using the mother code sequence.
9. The wireless device according to claim 8 , wherein n=n′−1, and the encoder obtaining, based on the sequence whose length is 2 n′ , the mother code sequence used for coding comprises the encoder configured to:
obtain the mother code sequence based on an even sequence number or an odd sequence number in the sequence whose length is 2 n′ .
10. The wireless device according to claim 8 , wherein that the encoder configured to obtain, based on the sequence whose length is 2 n′ , the mother code sequence used for coding comprises the encoder configured to:
obtain, based on the sequence whose length is 2 n′ , the mother code sequence used for coding, so that any sequence number S′ in the mother code sequence meets the following condition:
S
′
=
S
+
v
2
n
′
-
n
,
wherein
S is a sequence number that meets the following condition in the sequence whose length is 2 n′ :
mod
(
S
+
v
2
n
′
-
n
)
=
0
,
wherein
V is an integer, −2 n′-n <V≤0, and mod is a modulo operator.
11. The wireless device according to claim 8 , wherein the encoder configured to obtain, based on the sequence whose length is 2 n′ , the mother code sequence used for coding comprises the encoder configured to:
extract 2 n sequence numbers from the 2 n′ sequence numbers in the sequence whose length is 2 n′ , wherein n′−n bits at fixed locations in a binary form of each of the 2 n sequence numbers each are equal to a preset value; and wherein
the mother code sequence is formed based on a sequence represented by using remaining bits obtained after the n′−n bits at the fixed locations are removed from the binary form of each of the 2 n sequence numbers.
12. The wireless device according to claim 8 , wherein an order of the 2 n sequence numbers of the mother code sequence in the mother code sequence is the same as that in the sequence whose length is 2 n′ .
13. The wireless device according to claim 8 , wherein the sequence whose length is 2 n′ is one of a plurality of sequences of different lengths, and the encoder is further configured to obtain the sequence whose length is 2 n′ from the plurality of sequences of different lengths.
14. The wireless device according to claim 8 , wherein the 2 n′ sequence numbers are sequence numbers of 2 n′ channels, and the sequence whose length is 2 n′ is obtained after the sequence numbers of the 2 n′ channels are sorted based on channel reliability.
15. The wireless device according to claim 8 , wherein the wireless device further comprises an interface, and the encoder is configured to obtain the input to-be-coded bit through the interface.
16. A chip, comprising:
an interface; and
an encoder configured to:
obtain an input to-be-coded bit through the interface, and
obtain a mother code sequence used for coding from a sequence whose length is 2 n ′, wherein the sequence whose length is 2 n′ comprises 2 n′ sequence numbers, a length of the mother code sequence is 2 n , the mother code sequence comprises 2 n sequence numbers, the 2 n sequence numbers are a subset of the 2 n′ sequence numbers, n′ is a positive integer, and n is a positive integer less than or equal to n′, and
code the input to-be-coded bit by using the mother code sequence.
17. The chip according to claim 16 , wherein n=n′−1, and that the encoder is configured to obtain, based on the sequence whose length is 2 n′ , the mother code sequence used for coding comprises the encoder configured to:
obtain the mother code sequence based on an even sequence number or an odd sequence number in the sequence whose length is 2 n′ .
18. The chip according to claim 16 , wherein that the encoder is configured to obtain, based on the sequence whose length is 2 n′ , the mother code sequence used for coding comprises the encoder configured to:
obtain, based on the sequence whose length is 2 n′ , the mother code sequence used for coding, so that any sequence number S′ in the mother code sequence meets the following condition:
S
′
=
S
+
v
2
n
′
-
n
,
wherein
S is a sequence number that meets the following condition in the sequence whose length is 2 n′ :
mod
(
S
+
v
2
n
′
-
n
)
=
0
,
wherein
V is an integer, −2 n′-n <V≤0, and mod is a modulo operator.
19. The chip according to claim 16 , wherein the encoder configured to obtain, based on the sequence whose length is 2 n′ , the mother code sequence used for coding comprises the encoder configured to:
extract 2 n sequence numbers from the 2 n′ sequence numbers in the sequence whose length is 2 n′ , wherein n′−n bits at fixed locations in a binary form of each of the 2 n sequence numbers each are equal to a preset value; and wherein
the mother code sequence is formed based on a sequence represented by using remaining bits obtained after the n′−n bits at the fixed locations are removed from the binary form of each of the 2 n sequence numbers.
20. The chip according to claim 16 , wherein an order of the 2 n sequence numbers of the mother code sequence in the mother code sequence is the same as that in the sequence whose length is 2 n′ .Cited by (0)
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