US11193843B2ActiveUtilityA1

Capacitive pressure sensor

70
Assignee: SOORIAKUMAR KATHIRGAMASUNDARAMPriority: Feb 22, 2016Filed: Apr 9, 2020Granted: Dec 7, 2021
Est. expiryFeb 22, 2036(~9.6 yrs left)· nominal 20-yr term from priority
G01L 9/0045G01L 9/0073H05K 2201/10151B81C 1/00182H05K 3/4038H05K 3/4644H05K 1/18
70
PatentIndex Score
0
Cited by
29
References
17
Claims

Abstract

Aspects of the disclosure provide a capacitive pressure sensor. The capacitive pressure sensor can include a first substrate having a first surface and a second surface, a movable plate at a bottom of a first cavity recessed into the substrate from the first surface, and a second substrate bonded to the first substrate over the first surface. A second cavity is formed between the movable plate and the second surface. The second substrate includes a fixed plate disposed over the movable plate to form a capacitor. The second substrate further includes a third cavity between a surface of the fixed plate opposite to the movable plate and a surface of the second substrate opposite to the first substrate.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
       1. A process for fabricating a capacitive pressure sensor, comprising:
 forming a first cavity recessed into a first substrate from a first surface of the first substrate; 
 forming a first isolation layer over the first surface of the first substrate and a surface of the first cavity; 
 forming a diaphragm layer at the bottom of the first cavity over the first isolation layer; forming a second cavity recessed into a second substrate from a second surface of the second substrate; and 
 bonding the second substrate to the first substrate under the first surface of the first substrate with the first cavity adjacent to the second cavity. 
 
     
     
       2. The process of  claim 1 ,
 wherein the second substrate is a part of a silicon on insulator wafer and includes a second isolation layer, and further comprising: 
 forming a fixed plate layer between the second isolation layer and a bottom of the second cavity. 
 
     
     
       3. The process of  claim 2 , further comprising:
 forming damping holes on the fixed plate layer before bonding the second substrate to the first substrate. 
 
     
     
       4. The process of  claim 3 , further comprising:
 reducing the first substrate at a third surface of the first substrate opposite to the first surface of the substrate; 
 forming a third cavity beside the first isolation layer opposite to the first cavity in the first substrate; and 
 forming a fourth cavity beside the fixed plate layer opposite to the second cavity in the second substrate. 
 
     
     
       5. The process of  claim 4 , further comprising:
 removing a portion of the first isolation layer to form a movable diaphragm; and 
 removing a portion of the second isolation layer to form a fixed plate, wherein the movable diaphragm and the fixed plate form a capacitor. 
 
     
     
       6. The process of  claim 5 , further comprising:
 forming a via hole in the first substrate for electrical interconnection to the diaphragm layer after reducing the first substrate, the via hole having an opening at a fourth surface of the first substrate at a reduced side of the first substrate; and 
 forming an isolation wall surrounding the via hole, wherein the isolation wall and the first isolation layer forms an isolation well enclosing the via hole. 
 
     
     
       7. The process of  claim 6 , further including:
 attaching the second substrate to a package substrate; and 
 attaching a cap to the package substrate to enclose the first substrate and the second substrate, the cap having an opening. 
 
     
     
       8. The process of  claim 1 , wherein bonding the second substrate to the first substrate includes fusion bonding the second substrate to the first substrate. 
     
     
       9. The process of  claim 1 , wherein the diaphragm layer is constructed with silicon oxide or silicon carbide. 
     
     
       10. The process of  claim 1 , wherein the first substrate is a portion of a prime wafer or a test wafer. 
     
     
       11. A process for fabricating a capacitive pressure sensor, comprising:
 forming a first cavity recessed into a first substrate from a first surface of the first substrate; 
 forming a first isolation layer over the first surface of the first substrate and a surface of the first cavity; 
 forming a diaphragm layer at the bottom of the first cavity over the first isolation layer; 
 bonding a second substrate to the first surface of the first substrate; and 
 forming a plurality of through holes on the second substrate, the plurality of through holes being in registration with the first cavity allowing the first cavity to be in fluid communication with an exterior. 
 
     
     
       12. The process of  claim 11 , comprising:
 forming a second isolation layer on the second substrate before bonding the second substrate to the first substrate. 
 
     
     
       13. The process of  claim 12 , wherein the second substrate is bonded to the first substrate such that the second isolation layer is in-between the second substrate and the first substrate. 
     
     
       14. The process of  claim 11 , comprising:
 forming a second cavity recessed into the first substrate from a second surface of the first substrate, the second surface being on an opposite side to the first surface of the first substrate, the second cavity being in registration with the diaphragm layer. 
 
     
     
       15. The process of  claim 14 , wherein
 the second cavity is in fluid communication with an exterior. 
 
     
     
       16. The process of  claim 11 , comprising:
 forming a first electrical contact with the diaphragm layer. 
 
     
     
       17. The process of  claim 11 , comprising:
 forming a second electrical contact with the second substrate.

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