US11196682B2ActiveUtilityA1

IP aliases in logical networks with hardware switches

89
Assignee: NICIRA INCPriority: Sep 30, 2015Filed: Sep 20, 2019Granted: Dec 7, 2021
Est. expirySep 30, 2035(~9.2 yrs left)· nominal 20-yr term from priority
Inventors:Anupam Chanda
H04L 2101/622H04L 61/5007H04L 49/35H04L 61/103H04L 61/2007H04L 61/6022
89
PatentIndex Score
4
Cited by
203
References
20
Claims

Abstract

Some embodiments provide a novel method of configuring a managed hardware forwarding element (MHFE) that implements a logical forwarding element (LFE) of a logical network to handle address resolution requests (e.g., Address Resolution Protocol (ARP) requests) for multiple addresses (e.g., IP addresses) associated with a single network interface of the logical network. The method identifies a physical port of the MHFE with which the multiple addresses are to be associated. The physical port is coupled to an end machine (e.g., a virtual machine, server, container, etc.) of the logical network. The method then modifies associations stored at the MHFE to associate the physical port with the multiple addresses.

Claims

exact text as granted — not AI-modified
I claim: 
     
       1. A method for associating a set of addresses with a logical network interface in a logical network, the logical network implemented by a set of hardware forwarding elements, the method comprising:
 identifying a plurality of logical addresses assigned to a machine of the logical network, the machine attached to a particular port of a particular hardware forwarding element of the set of hardware forwarding elements; 
 identifying a particular address that receives the most network traffic of the plurality of logical addresses assigned to the machine; and modifying a set of associations stored at the particular hardware forwarding element to associate the particular port with the particular address. 
 
     
     
       2. The method of  claim 1 , wherein identifying the plurality of logical addresses comprises receiving input that assigns the logical addresses to the machine. 
     
     
       3. The method of  claim 1 , wherein the logical addresses are Internet Protocol (IP) addresses. 
     
     
       4. The method of  claim 1 , wherein the set of associations are used by the particular hardware forwarding element to map the particular address to a data link layer address when performing address resolution. 
     
     
       5. The method of  claim 1 , wherein the particular hardware forwarding element is a top-of-rack (TOR) switch in a rack and the particular port of the TOR switch is coupled to a rack server on the rack. 
     
     
       6. The method of  claim 1 , wherein the set of associations maps the particular port to a logical switch of a plurality of logical switches that are implemented by the particular hardware forwarding element. 
     
     
       7. The method of  claim 1 , wherein the set of associations are used by the particular hardware forwarding element to perform address resolution protocol (ARP) suppression for the machine of the logical network. 
     
     
       8. The method of  claim 1 , wherein the method is performed by a network controller, wherein modifying the set of associations comprises configuring a configuration database of the particular hardware forwarding element. 
     
     
       9. The method of  claim 1  further comprising monitoring frequency of traffic to each of the plurality of logical addresses, the monitored frequency of traffic used to identify the particular address. 
     
     
       10. The method of  claim 1 , wherein the network traffic for each of the logical addresses is measured based on a number of packets received. 
     
     
       11. A non-transitory machine readable medium storing a program which when executed by at least one processing unit associates a set of addresses with a logical network interface in a logical network, the logical network implemented by a set of hardware forwarding elements, the program comprising sets of instructions for:
 identifying a plurality of logical addresses assigned to a machine of the logical network, the machine attached to a particular port of a particular hardware forwarding element of the set of hardware forwarding elements; 
 identifying a particular address that receives the most network traffic of the plurality of logical addresses assigned to the machine; and 
 modifying a set of associations stored at the particular hardware forwarding element to associate the particular port with the particular address. 
 
     
     
       12. The non-transitory machine readable medium of  claim 11 , wherein the set of instructions for identifying the plurality of logical addresses comprises a set of instructions for receiving input that assigns the logical addresses to the machine. 
     
     
       13. The non-transitory machine readable medium of  claim 11 , wherein the logical addresses are Internet Protocol (IP) addresses. 
     
     
       14. The non-transitory machine readable medium of  claim 11 , wherein the set of associations are used by the particular hardware forwarding element to map the particular address to a data link layer address when performing address resolution. 
     
     
       15. The non-transitory machine readable medium of  claim 11 , wherein the particular hardware forwarding element is a top-of-rack (TOR) switch in a rack and the particular port of the TOR switch is coupled to a rack server on the rack. 
     
     
       16. The non-transitory machine readable medium of  claim 11 , wherein the set of associations maps the particular port to a logical switch of a plurality of logical switches that are implemented by the particular hardware forwarding element. 
     
     
       17. The non-transitory machine readable medium of  claim 11 , wherein the set of associations are used by the particular hardware forwarding element to perform address resolution protocol (ARP) suppression for the machine of the logical network. 
     
     
       18. The non-transitory machine readable medium of  claim 11 , wherein the set of instructions for modifying the set of associations comprises a set of instructions for configuring a configuration database of the particular hardware forwarding element. 
     
     
       19. The non-transitory machine readable medium of  claim 11 , wherein the program further comprises a set of instructions for monitoring frequency of traffic to each of the plurality of logical addresses, the monitored frequency of traffic used to identify the particular address. 
     
     
       20. The non-transitory machine readable medium of  claim 11 , wherein the network traffic for each of the logical addresses is measured based on a number of packets received.

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