Serdes equalization for short, reflective channels

Abstract

An illustrative short, high-rate communications link includes a serializer that provides a signal having a symbol rate of at least 10 GHz; and a deserializer that receives the signal via a printed circuit board (“PCB”) trace coupled to the serializer with a first impedance mismatch and coupled to the deserializer with a second impedance mismatch. At least one of the serializer and deserializer includes an equalizer that attenuates a frequency component of the signal at half of the symbol rate relative to a frequency component of the signal at one third of the symbol rate. Though such attenuation may reduce signal-to-noise ratio, an improved communications performance may nevertheless be achieved by suppression of signal reflections.

What is claimed is: 
     
       1. A short, high-rate communications link that comprises:
 a serializer that provides a signal having a symbol rate; and 
 a deserializer that receives the signal via a printed circuit board (“PCB”) trace, the PCB trace being coupled to the serializer with a first impedance mismatch and coupled to the deserializer with a second impedance mismatch, the deserializer operating to convert the signal into a symbol stream, 
 at least one of the serializer and deserializer including an equalizer that attenuates a frequency component of the signal at half of the symbol rate relative to a frequency component of the signal at one third of the symbol rate. 
 
     
     
       2. The communications link of  claim 1 , wherein a length of the PCB trace is between 2.5 cm and 25 cm, and wherein the first impedance mismatch is a connection of the PCB trace to a packaged integrated circuit chip that includes the serializer and the second impedance mismatch is a connection of the PCB trace to a connector mating with a network interface module that includes the deserializer. 
     
     
       3. The communications link of  claim 1 , wherein the equalizer is a digital domain pre-equalizer having a post-cursor coefficient (C 1 ) greater than a magnitude of a pre-cursor coefficient (C −1 ). 
     
     
       4. The communications link of  claim 1 , wherein the equalizer is a digital domain pre-equalizer having a post-cursor coefficient (C 1 ) greater than an alternate-polarity sum of the pre-equalizer's pre-cursor coefficients: Σ i<0 (−1) i C i . 
     
     
       5. The communications link of  claim 4 , wherein the deserializer includes a decision feedback equalizer that at least partially compensates for trailing intersymbol interference caused by the post-cursor coefficient. 
     
     
       6. The communications link of  claim 1 , wherein the equalizer is a continuous time linear equalizer. 
     
     
       7. A serializer that comprises:
 a pre-equalizer that produces a filtered data stream having a symbol rate, the filtered data stream having a frequency component at the half of the symbol rate that the pre-equalizer attenuates relative to a frequency component at one third of the symbol rate; and 
 a driver that converts the filtered data stream into a transmit signal. 
 
     
     
       8. The serializer of  claim 7 , wherein the pre-equalizer is a digital domain filter having a post-cursor coefficient (C 1 ) greater than a magnitude of a pre-cursor coefficient (C −1 ). 
     
     
       9. The serializer of  claim 7 , wherein the pre-equalizer is a digital domain filter having a post-cursor coefficient (C 1 ) greater than an alternate-polarity sum of the pre-equalizer's pre-cursor coefficients: Σ i<0 (−1) i C i . 
     
     
       10. A deserializer that comprises:
 at least one of a continuous time linear equalizer and a digital domain linear equalizer to convert a received signal having a symbol rate into an equalized signal with a frequency component at half of the symbol rate attenuated relative to a frequency component at one third of the symbol rate; 
 a decision feedback equalizer that converts the equalized signal into a symbol stream; and 
 a controller that combines the equalized signal with the symbol stream or with a predetermined training sequence to evaluate a channel reflection strength and, if the channel reflection strength exceeds a threshold, to enable artificial attenuation of a frequency component of the received signal at half of the symbol rate relative to a received signal frequency component at one third of the symbol rate. 
 
     
     
       11. The deserializer of  claim 10 , wherein the controller enables the artificial attenuation by adjusting a pole frequency of the continuous time linear equalizer. 
     
     
       12. The deserializer of  claim 10 , wherein the controller enables the artificial attenuation by adjusting a post-cursor coefficient of the digital domain linear equalizer. 
     
     
       13. The deserializer of  claim 10 , wherein the controller enables the artificial attenuation by providing backchannel information to a source of the received signal, the backchannel information adjusting a post-cursor coefficient of a pre-equalizer at the source. 
     
     
       14. The deserializer of  claim 10 , wherein the controller enables the artificial attenuation by reducing a bandwidth of a transmit driver. 
     
     
       15. A communications method that comprises:
 providing a communication channel to convey a signal from a serializer to a deserializer, the signal having a symbol rate; 
 characterizing a reflection strength in the communication channel; and 
 configuring the serializer to attenuate or boost a frequency component of the signal at half of the symbol rate relative to a frequency component at one third of the symbol rate based on whether the reflection strength exceeds a predetermined threshold. 
 
     
     
       16. The communications method of  claim 15 , further comprising configuring the deserializer to also attenuate or boost the frequency component at half of the symbol rate based on whether the reflection strength exceeds the predetermined threshold. 
     
     
       17. The communications method of  claim 16 , wherein said configuring the deserializer includes reducing a pole frequency of a continuous time linear equalizer if the reflection strength exceeds the threshold. 
     
     
       18. The communications method of  claim 17 , wherein said configuring the deserializer includes making a post-cursor coefficient of a digital domain linear equalizer greater than an alternate-polarity sum of the equalizer's pre-cursor coefficients: Σ i<0 (−1) i C i . 
     
     
       19. The communications method of  claim 15 , wherein said configuring the serializer includes making a post-cursor coefficient of a digital domain linear equalizer greater than an alternate-polarity sum of the equalizer's pre-cursor coefficients: Σ i<0 (−1) i C i . 
     
     
       20. The communications method of  claim 15 , wherein said configuring the serializer includes adjusting a bandwidth of a transmit driver. 
     
     
       21. A communications method that comprises:
 receiving a signal having a symbol rate via a communication channel from a serializer; 
 characterizing a reflection strength in the communication channel; and 
 configuring an equalizer in a deserializer to attenuate or boost a frequency component of the signal at half of the symbol rate relative to a frequency component at one third of the symbol rate based on whether the reflection strength exceeds a predetermined threshold. 
 
     
     
       22. The communications method of  claim 21 , wherein said configuring the equalizer includes reducing a pole frequency of a continuous time linear equalizer if the reflection strength exceeds the threshold. 
     
     
       23. The communications method of  claim 21 , wherein said configuring the equalizer includes making a post-cursor coefficient (C 1 ) of a digital domain linear equalizer greater than a magnitude of a pre-cursor coefficient (C −1 ). 
     
     
       24. The communications method of  claim 21 , wherein said configuring the equalizer includes making a post-cursor coefficient (C 1 ) of a digital domain linear equalizer greater than an alternate-polarity sum of the equalizer's pre-cursor coefficients: Σ i<0 (−1) i C i .