Partition wire assignment for routing multi-partition circuit designs

Abstract

Performing partition wire assignment for routing a multi-partition circuit design can include performing, using computer hardware, a global assignment phase by clustering a plurality of super-long lines (SLLs) into a plurality of SLL bins, clustering loads of nets of a circuit design into a plurality of load clusters, and assigning the plurality of SLL bins to the plurality of load clusters. For each SLL bin, a detailed assignment phase can be performed wherein each net having a load cluster assigned to the SLL bin is assigned one or more particular SLLs of the SLL bin using the computer hardware.

What is claimed is: 
     
       1. A method, comprising:
 performing, using computer hardware, a global assignment phase by clustering a plurality of super-long lines (SLLs) into a plurality of SLL bins, clustering loads of nets of a circuit design into a plurality of load clusters, and assigning the plurality of SLL bins to the plurality of load clusters; and 
 for each SLL bin, performing a detailed assignment phase wherein each net having a load cluster assigned to the SLL bin is assigned one or more particular SLLs of the SLL bin using the computer hardware. 
 
     
     
       2. The method of  claim 1 , wherein the clustering includes:
 for each net, dividing a region of circuitry including the loads of the net into a number of sub-regions corresponding to a maximum number of load clusters allowed for the net and creating a load cluster for each sub-region that includes at least one load of the net. 
 
     
     
       3. The method of  claim 1 , further comprising:
 merging two or more SLL clusters during the global assignment phase. 
 
     
     
       4. The method of  claim 1 , further comprising:
 during the global assignment phase, performing at least one of wirelength optimization, congestion optimization, or timing optimization. 
 
     
     
       5. The method of  claim 1 , further comprising:
 processing a first cut of the circuit design and a second cut of the circuit design by performing the global assignment phase for each of the first cut and the second cut prior to performing a detailed assignment phase on the first cut or the second cut. 
 
     
     
       6. The method of  claim 5 , further comprising:
 for a selected net that spans the first cut and the second cut, projecting a load cluster corresponding to the second cut of the selected net from a super logic region (SLR) into a different SLR for use during the global assignment phase for the first cut. 
 
     
     
       7. The method of  claim 6 , wherein the selected net has a driver in a SLR, a first load cluster in a second SLR, and a second load cluster in a third SLR, the method comprising:
 projecting the second load cluster to a location in the second SLR for performing the global assignment phase for the first cut. 
 
     
     
       8. The method of  claim 1 , wherein:
 for each SLL bin, the one or more particular SLLs of the SLL bin are assigned to nets having a load cluster assigned to the SSL bin using a selected detailed assignment technique selected from a plurality of detailed assignment techniques based on timing criticality of the SLL bin. 
 
     
     
       9. The method of  claim 8 , wherein:
 timing criticality of the SLL bin is determined using a reference SLL of the SLL bin to represent timing characteristics of each SLL of the SLL bin. 
 
     
     
       10. The method of  claim 9 , wherein:
 a first detailed assignment technique of the plurality of detailed assignment techniques includes, for a selected SLL bin, assigning nets having a load cluster assigned to the selected SLL bin to an SLL of the selected SLL bin based on wirelength displacement of the nets of the selected SLL bin; and 
 a second detailed assignment technique of the plurality of detailed assignment techniques includes, for a selected SLL bin, modeling assignment of nets having a load cluster assigned to the selected SLL bin as a bottleneck assignment problem, generating an Integer Linear Programming formulation, and solving the Integer Linear Programming formulation. 
 
     
     
       11. A system, comprising:
 a processor configured to initiate operations including:
 performing a global assignment phase by clustering a plurality of super-long lines (SLLs) into a plurality of SLL bins, clustering loads of nets of a circuit design into a plurality of load clusters, and assigning the plurality of SLL bins to the plurality of load clusters; and 
 for each SLL bin, performing a detailed assignment phase wherein each net having a load cluster assigned to the SLL bin is assigned one or more particular SLLs of the SLL bin. 
 
 
     
     
       12. The system of  claim 11 , wherein the clustering includes:
 for each net, dividing a region of circuitry including the loads of the net into a number of sub-regions corresponding to a maximum number of load clusters allowed for the net and creating a load cluster for each sub-region that includes at least one load of the net. 
 
     
     
       13. The system of  claim 11 , wherein the processor is further configured to initiate operations comprising:
 merging two or more SLL clusters during the global assignment phase. 
 
     
     
       14. The system of  claim 11 , wherein the processor further is configured to initiate operations comprising:
 during the global assignment phase, performing at least one of wirelength optimization, congestion optimization, or timing optimization. 
 
     
     
       15. The system of  claim 11 , wherein the processor is further configured to initiate operations comprising:
 processing a first cut of the circuit design and a second cut of the circuit design by performing the global assignment phase for each of the first cut and the second cut prior to performing a detailed assignment phase on the first cut or the second cut. 
 
     
     
       16. The system of  claim 15 , wherein the processor is further configured to initiate operations comprising:
 for a selected net that spans the first cut and the second cut, projecting a load cluster corresponding to the second cut of the selected net from a super logic region (SLR) into a different SLR for use during the global assignment phase for the first cut. 
 
     
     
       17. The system of  claim 16 , wherein the selected net has a driver in a first SLR, a first load cluster in a second SLR, and a second load cluster in a third SLR, and wherein the processor is configured to initiate operations comprising:
 projecting the second load cluster to a location in the second SLR for performing the global assignment phase for the first cut. 
 
     
     
       18. The system of  claim 11 , wherein:
 for each SLL bin, the one or more particular SLLs of the SLL bin are assigned to nets having a load cluster assigned to the SLL bin using a selected detailed assignment technique selected from a plurality of detailed assignment techniques based on timing criticality of the SLL bin. 
 
     
     
       19. The system of  claim 18 , wherein:
 a first detailed assignment technique of the plurality of detailed assignment techniques includes, for a selected SLL bin, assigning nets having a load cluster assigned to the selected SLL bin to an SLL of the selected SLL bin based on wirelength displacement of the nets of the selected SLL bin; and 
 a second detailed assignment technique of the plurality of detailed assignment techniques includes, for a selected SLL bin, modeling assignment of nets having a load cluster assigned to the selected SLL bin as a bottleneck assignment problem, generating an Integer Linear Programming formulation, and solving the Integer Linear Programming formulation. 
 
     
     
       20. A computer program product, comprising:
 one or more computer readable storage media, and program instructions collectively stored on the one or more computer readable storage media, wherein the program instructions are executable by computer hardware to initiate operations including:
 performing a global assignment phase by clustering a plurality of super-long lines (SLLs) into a plurality of SLL bins, clustering loads of nets of a circuit design into a plurality of load clusters, and assigning the plurality of SLL bins to the plurality of load clusters; and 
 for each SLL bin, performing a detailed assignment phase wherein each net having a load cluster assigned to the SLL bin is assigned one or more particular SLLs of the SLL bin.