Pixel and display device including the same

Abstract

The present embodiments disclose a pixel and a display device including the same. A pixel according to an embodiment of the present disclosure includes a luminous element and a pixel circuit connected to the luminous element, wherein the pixel circuit includes a first pixel circuit configured to control light-emission and non-emission of the luminous element in response to a control signal applied to each of a plurality of subframes constituting a frame during a light-emitting period and a second pixel circuit storing a bit value of image data in a data writing period and generating the control signal based on the bit value and a clock signal in the light-emitting period.

The invention claimed is: 
     
       1. A pixel comprising:
 a luminous element; and 
 a pixel circuit connected to the luminous element and comprising:
 a first pixel circuit configured to control light-emission and non-emission of the luminous element in response to a control signal applied to each of a plurality of subframes constituting a frame; and 
 a second pixel circuit configured to store bit values of image data in the frame, and generate the control signal based on the stored bit values and a clock signal such that each subframe included in the frame is controlled according to each bit value. 
 
 
     
     
       2. The pixel of  claim 1 , wherein the first pixel circuit includes:
 a first transistor configured to output a driving current; and 
 a second transistor configured to transmit or block the driving current to the luminous element according to the control signal. 
 
     
     
       3. The pixel of  claim 2 , wherein the first pixel circuit includes a level shifter that converts a voltage level of the control signal. 
     
     
       4. The pixel of  claim 2 , wherein the first transistor constitutes a current mirror circuit, together with an external circuit of the pixel. 
     
     
       5. The pixel of  claim 1 , wherein the second pixel circuit includes:
 a memory configured to store the bit values of the image data; and 
 a pulse width modulation (PWM) controller configured to read the bit values from the memory and determine a pulse width of the control signal for a subframe based on a length of the subframe and a bit value corresponding to the subframe. 
 
     
     
       6. A display device comprising:
 a pixel unit including a plurality of pixels, each including a luminous element and a pixel circuit connected to the luminous element; 
 a current supply unit configured to supply a driving current to the plurality of pixels; and 
 a clock generator configured to supply a clock signal to the plurality of pixels when each of a plurality of subframes constituting a frame starts, 
 wherein the pixel circuit of each pixel includes:
 a first pixel circuit controlling light-emission and non-emission of the luminous element in response to a control signal applied for each of the subframes and 
 a second pixel circuit configured to store bit values of image data in the frame, and generate the control signal based on the stored bit values and the clock signal such that each subframe included in the frame is controlled according to each bit value. 
 
 
     
     
       7. The display device of  claim 6 , wherein the first pixel circuit includes:
 a first transistor configured to output a driving current; and 
 a second transistor configured to transmit or block the driving current to the luminous element according to the control signal. 
 
     
     
       8. The display device of  claim 7 , wherein the first pixel circuit further includes a level shifter converting a voltage level of the control signal. 
     
     
       9. The display device of  claim 7 , wherein the first transistor constitutes a current mirror circuit, together with an external circuit. 
     
     
       10. The display device of  claim 6 , wherein the second pixel circuit includes:
 a memory configured to store the bit values of the image data; and 
 a pulse width modulation (PWM) controller configured to read the bit values from the memory and determine a pulse width of the control signal for a subframe based on a length of the subframe and a bit value corresponding to the subframe.