Codeword concatenation for correcting errors in data storage devices

Abstract

Various implementations described herein relate to systems and methods for encoding and decoding data having input payload stored in a non-volatile storage device, including encoding the input payload by concatenating a plurality of short codewords to generate a plurality of encoded short codewords, and decoding the plurality of encoded short codewords to obtain the data, where each of the plurality of short codewords corresponding to a portion of the input payload.

What is claimed is: 
     
       1. A method for encoding and decoding data having input payload stored in a non-volatile storage device, comprising:
 encoding the input payload by concatenating a plurality of short codewords to generate a plurality of encoded short codewords, each of the plurality of short codewords corresponding to a portion of the input payload, wherein each of the plurality of short codewords has a different code rate; and 
 decoding the plurality of encoded short codewords to obtain the data. 
 
     
     
       2. The method of  claim 1 , wherein generating the long codeword by concatenating the plurality of short codewords comprises:
 determining a first signature using a first input payload of a first short codeword of the plurality of short codewords, the first short codeword comprises the first input payload and the first signature; 
 determining first redundancy bits by encoding the first short codeword using a first encoding scheme, a first encoded short codeword comprises the first input payload, the first signature, and the first redundancy bits; 
 selecting, from the first encoded short codeword, a first set of bits; 
 concatenating the first set of bits to a second input payload of a second short codeword of the plurality of short codewords; 
 determining a second signature using the first set of bits and the second input payload, the second short codeword comprises the second input payload and the second signature; and 
 determining second redundancy bits by encoding the second short codeword using a second encoding scheme, a second encoded short codeword comprises the second input payload, the second signature, and the second redundancy bits. 
 
     
     
       3. The method of  claim 2 , wherein generating the long codeword by concatenating the plurality of short codewords further comprises:
 selecting, from the second encoded short codeword, a second set of bits; 
 concatenating the second set of bits to a third input payload of a third short codeword of the plurality of short codewords; 
 determining a third signature using the second set of bits and the third input payload, the third short codeword comprises the third input payload and the third signature; and 
 determining third redundancy bits by encoding the third short codeword using a third encoding scheme, a third encoded short codeword comprises the third input payload, the third signature, and the third redundancy bits. 
 
     
     
       4. The method of  claim 2 , wherein each of the first signature and the second signature is a cyclic redundancy check-sum (CRC). 
     
     
       5. The method of  claim 2 , wherein
 the first codeword has a first code rate; 
 the second codeword has a second code rate; and 
 the second code rate is higher than the first code rate. 
 
     
     
       6. The method of  claim 2 , wherein each of the encoding scheme and the second encoding scheme is a half folded-product code (HFPC) encoding scheme. 
     
     
       7. The method of  claim 1 , wherein generating the long codeword by concatenating the plurality of short codewords comprises allocating a redundancy size for each of the plurality of short codewords. 
     
     
       8. The method of  claim 7 , wherein the redundancy size for each of the plurality of short codewords is a total redundancy size of the long codeword divided by a number of the plurality of short codewords. 
     
     
       9. The method of  claim 1 , wherein generating the long codeword by concatenating the plurality of short codewords comprises:
 determining a first signature using a first input payload of a first short codeword of the plurality of short codewords, the first short codeword comprises the first input payload and the first signature; 
 determining first redundancy bits by encoding the first short codeword using a first encoding scheme, a first encoded short codeword comprises the first input payload, the first signature, and the first redundancy bits; 
 selecting, from the first redundancy bits, a first set of bits; 
 concatenating the first set of bits to a second input payload of a second short codeword of the plurality of short codewords; 
 determining a second signature using the first set of bits and the second input payload, the second short codeword comprises the second input payload and the second signature; and 
 determining second redundancy bits by encoding the second short codeword using a second encoding scheme, a second encoded short codeword comprises the second input payload, the second signature, and the second redundancy bits. 
 
     
     
       10. The method of  claim 1 , wherein the plurality of encoded short codewords is decoded using one or more of decoding methods, the decoding methods comprise partial decoding, successive decoding, and joint decoding. 
     
     
       11. The method of  claim 10 , wherein decoding the plurality of encoded short codewords comprises:
 decoding the plurality of encoded short codewords using a first decoding method of the decoding methods; 
 in response to determining that the first decoding method fails, decoding the plurality of encoded short codewords using a second decoding method of the decoding methods; and 
 in response to determining that the second decoding method fails, decoding the plurality of encoded short codewords using a third decoding method of the decoding methods. 
 
     
     
       12. The method of  claim 10 , wherein decoding the plurality of encoded short codewords comprises determining whether to perform the one or more of the decoding methods in a hard decoding mode or a soft decoding mode based on one or more of tail latency distribution or NAND stress condition of the non-volatile storage device. 
     
     
       13. An error correction system, comprising:
 a processing circuit configured to encode and decode data having input payload stored in a non-volatile storage device by:
 encoding the input payload by concatenating a plurality of short codewords to generate a plurality of encoded short codewords, each of the plurality of short codewords corresponding to a portion of the input payload, wherein each of the plurality of short codewords has a different code rate; and 
 decoding the plurality of encoded short codewords to obtain the data. 
 
 
     
     
       14. The error correction system of  claim 13 , wherein the processing circuit generates the long codeword by:
 determining a first signature using a first input payload of a first short codeword of the plurality of short codewords, the first short codeword comprises the first input payload and the first signature; determining first redundancy bits by encoding the first short codeword using a first encoding scheme, a first encoded short codeword comprises the first input payload, the first signature, and the first redundancy bits; 
 selecting, from the first encoded short codeword, a first set of bits; 
 concatenating the first set of bits to a second input payload of a second short codeword of the plurality of short codewords; 
 determining a second signature using the first set of bits and the second input payload, the second short codeword comprises the second input payload and the second signature; and 
 determining second redundancy bits by encoding the second short codeword using a second encoding scheme, a second encoded short codeword comprises the second input payload, the second signature, and the second redundancy bits. 
 
     
     
       15. The error correction system of  claim 14 , wherein each of the encoding scheme and the second encoding scheme is a half folded-product code (HFPC) encoding scheme. 
     
     
       16. The error correction system of  claim 13 , wherein the plurality of encoded short codewords is decoded using one or more of decoding methods, the decoding methods comprise partial decoding, successive decoding, and joint decoding. 
     
     
       17. The error correction system of  claim 16 , wherein the processing circuit decodes the plurality of encoded short codewords by:
 decoding the plurality of encoded short codewords using a first decoding method of the decoding methods; 
 in response to determining that the first decoding method fails, decoding the plurality of encoded short codewords using a second decoding method of the decoding methods; and 
 in response to determining that the second decoding method fails, decoding the plurality of encoded short codewords using a third decoding method of the decoding methods. 
 
     
     
       18. A non-transitory computer-readable medium storing computer-readable instructions, such that when executed, causes a processing circuit to:
 encode an input payload by concatenating a plurality of short codewords to generate a plurality of encoded short codewords, each of the plurality of short codewords corresponding to a portion of the input payload, wherein each of the plurality of short codewords has a different code rate; and 
 decode the plurality of encoded short codewords to obtain the data.