US11266020B1ActiveUtility

Electronic assemblies having components with edge connectors

94
Assignee: VICOR CORPPriority: Jan 14, 2015Filed: Apr 26, 2021Granted: Mar 1, 2022
Est. expiryJan 14, 2035(~8.5 yrs left)· nominal 20-yr term from priority
B23K 1/0016H05K 1/0209H05K 1/0298H05K 2201/1034H05K 2201/10166B23K 1/0008B23K 2101/42B23K 1/20H05K 3/284H05K 3/36H05K 3/303H05K 1/181H05K 2203/1316H05K 7/20409H05K 1/141
94
PatentIndex Score
2
Cited by
78
References
29
Claims

Abstract

Circuit assemblies can be electrically interconnected by providing a circuit assembly having a top surface, a bottom surface, and a perimeter edge connecting the top and bottom surfaces, the perimeter edge being formed of insulative material and having a plurality of conductive features embedded in and exposed on the surface of the edge. The conductive features are arranged in contact sets, and each contact set is separated from adjacent contact sets by a portion of the perimeter edge that is free of conductive features. Each contact set includes conductive features that together form a distributed electrical connection to a single node. The insulative material is selectively removed to form recesses adjacent the conductive features exposing additional surface contact areas along lateral portions of the conductive features in the recesses.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
       1. A method of electrically interconnecting circuit assemblies, the method comprising:
 providing a circuit assembly having a top surface, a bottom surface, and a perimeter edge connecting the top and bottom surfaces, the perimeter edge being formed of insulative material and having a plurality of conductive features embedded in the surface of the perimeter edge, the conductive features each including an exposed edge, the exposed edges being arranged into one or more contact sets, 
 each contact set providing an electrical connection to a respective electrical node of the circuit assembly, comprising one or more of the conductive features, being separated from adjacent contact sets by a portion of the perimeter edge that is free of conductive features, and being located at an elevation in the perimeter surface between the bottom surface and the top surface; and 
 selectively removing portions of the insulative material from the surface of the perimeter edge adjacent to selected ones of the exposed edges of selected ones of the conductive features exposing additional surface area of the selected ones of the conductive features, 
 wherein the additional surface area is recessed from the perimeter edge and together with the adjacent exposed edge forms a three dimensional contact. 
 
     
     
       2. The method of  claim 1  wherein the additional surface area forms an angle greater than 45 degrees to the perimeter edge. 
     
     
       3. The method of  claim 1 , further comprising preparing the additional surface area of the conductive features for solder wetting. 
     
     
       4. The method of  claim 1 , further comprising applying solder paste to the exposed portions of the conductive features. 
     
     
       5. The method of  claim 1 , further comprising wetting the conductive features in the recesses and along the perimeter surface with solder. 
     
     
       6. The method of  claim 1 , further comprising placing an external conductive terminal adjacent the conductive features and forming a solder connection between the external conductive terminal and the conductive features. 
     
     
       7. The method of  claim 1 , further comprising forming a solder connection between each set of the conductive features and a respective conductive pad on a printed circuit board. 
     
     
       8. The method of  claim 1 , further comprising forming a solder connection between each set of the conductive features and a respective terminal of a lead frame. 
     
     
       9. The method of  claim 1  wherein the elevation is approximately midway between the top and bottom surfaces. 
     
     
       10. The method of  claim 1  wherein the selective removing comprises plasma etching. 
     
     
       11. The method of  claim 1  wherein the selective removing comprises removing approximately 2.5 to 3.5 mils of the insulative material. 
     
     
       12. The method of  claim 1  wherein the selective removing comprises masking portions of the circuit assembly. 
     
     
       13. The method of  claim 1 , comprising forming a plurality of three dimensional contacts, arranging the three dimensional contacts in a plurality of contact sets, each contact set having a plurality of three dimensional contacts, wherein each contact set is separated from adjacent contact sets by a portion of the external perimeter edge that is free of conductive features, and using the plurality of three dimensional contacts of each contact set together to form a distributed electrical connection to a single electrical node in the circuit assembly. 
     
     
       14. The method of  claim 1  wherein the circuit assembly comprises a printed circuit board (“PCB”) having a plurality of conductive layers, the PCB being located at an elevation in the perimeter surface between the first surface and the second surface, at least one of the first and second surfaces comprise a cured encapsulant material, and the conductive features comprise selected portions of the conductive layers of the PCB. 
     
     
       15. The method of  claim 14  wherein selectively removing portions of material from the perimeter surface comprises plasma etching portions of the material in insulation layers in the PCB. 
     
     
       16. The method of  claim 15  wherein selectively removing portions of material from the perimeter surface further comprises media blasting the plasma etched portions. 
     
     
       17. The method of  claim 16  wherein the media blasting uses dry ice as a blasting media. 
     
     
       18. The method of  claim 10  wherein the selective removing comprises masking portions of the circuit assembly. 
     
     
       19. The method of  claim 18  wherein the circuit assembly comprises a printed circuit board (“PCB”) having a plurality of conductive layers, at least one of the first and second surfaces comprise a cured encapsulant material, and the conductive features comprise selected portions of the conductive layers of the PCB. 
     
     
       20. The method of  claim 19  wherein selectively removing portions of material from the perimeter surface comprises plasma etching portions of the material in insulation layers in the PCB. 
     
     
       21. The method of  claim 20  wherein selectively removing portions of material from the perimeter surface further comprises media blasting the plasma etched portions. 
     
     
       22. The method of  claim 21  wherein the media blasting uses dry ice as a blasting media. 
     
     
       23. The method of  claim 21 , comprising forming a plurality of three dimensional contacts, arranging the three dimensional contacts in a plurality of contact sets, each contact set having a plurality of three dimensional contacts, wherein each contact set is separated from adjacent contact sets by a portion of the external perimeter edge that is free of conductive features, and using the plurality of three dimensional contacts of each contact set together to form distributed electrical connections to the circuit assembly. 
     
     
       24. The method of  claim 21 , further comprising preparing the additional surface area of the conductive features for solder wetting. 
     
     
       25. The method of  claim 23 , further comprising applying solder paste to the exposed portions of the conductive features. 
     
     
       26. The method of  claim 21 , further comprising wetting the conductive features in the recesses and along the perimeter surface with solder. 
     
     
       27. The method of  claim 21 , further comprising placing an external conductive terminal adjacent the conductive features and forming a solder connection between the external conductive terminal and the conductive features. 
     
     
       28. The method of  claim 21 , further comprising forming a solder connection between each set of the conductive features and a respective conductive pad on a printed circuit board. 
     
     
       29. The method of  claim 23 , further comprising forming a solder connection between each set of the conductive features and a respective terminal of a lead frame.

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