Array substrate, manufacturing method thereof, and display panel

Abstract

The disclosure relates to an array substrate, a manufacturing method thereof, and a display panel. In one aspect, an organic layer is disposed in a display area to release applied forces generated when the array substrate is frequently bent. In another aspect, without adding additional mask sheets, a portion of the organic material in a recess is removed by using a halftone mask, an organic material in other areas of the display area is completely removed, and an organic material of a photoresist layer in a bending area is retained. Therefore, a surface of the organic layer away from the substrate aligns with a surface of the interlayer insulating layer away from the substrate, so that there is no height difference when a top source/drain layer is disposed.

What is claimed is: 
     
       1. An array substrate, comprising a display area and a bending area;
 wherein the array substrate comprises: 
 a substrate; 
 a barrier layer disposed on the substrate; 
 an insulating layer disposed on the barrier layer; 
 a plurality of conductive layers spaced apart from each other in the insulating layer; and 
 an interlayer insulating layer disposed on the conductive layers; 
 wherein in the display area, a depressed surface of the interlayer insulating layer away from the substrate reaches the barrier layer to form a recess, and the recess is filled with an organic material to form an organic layer; and 
 a surface of the organic layer away from the substrate aligns with a surface of the interlayer insulating layer away from the substrate. 
 
     
     
       2. The array substrate of  claim 1 , further comprising:
 a buffer layer disposed between the barrier layer and the insulating layer, wherein the organic layer penetrates through the buffer layer; 
 an active layer disposed between the buffer layer and the insulating layer; 
 a source/drain layer disposed on the interlayer insulating layer, wherein the source/drain layer is connected to the active layer by a through hole; and 
 a planarization layer disposed on the source/drain layer. 
 
     
     
       3. The array substrate of  claim 1 , wherein the insulating layer comprises a first gate insulating layer and a second gate insulating layer, and each of the conductive layers comprises a first gate layer and a second gate layer; and
 the first gate insulating layer is disposed on the barrier layer, the first gate layer is disposed on the first gate insulating layer, the second gate insulating layer is disposed on the first gate layer, the second gate layer is disposed on the second gate insulating layer, and the interlayer insulating layer is disposed on the second gate layer. 
 
     
     
       4. A display panel, comprising the array substrate of  claim 1 . 
     
     
       5. The display panel of  claim 4 , further comprising:
 a buffer layer disposed between the barrier layer and the insulating layer, wherein the organic layer penetrates through the buffer layer; 
 an active layer disposed between the buffer layer and the insulating layer; 
 a source/drain layer disposed on the interlayer insulating layer, wherein the source/drain layer is connected to the active layer by a through hole; and 
 a planarization layer disposed on the source/drain layer. 
 
     
     
       6. The display panel of  claim 4 , wherein the insulating layer comprises a first gate insulating layer and a second gate insulating layer, and each of the conductive layers comprises a first gate layer and a second gate layer; and
 the first gate insulating layer is disposed on the barrier layer, the first gate layer is disposed on the first gate insulating layer, the second gate insulating layer is disposed on the first gate layer, the second gate layer is disposed on the second gate insulating layer, and the interlayer insulating layer is disposed on the second gate layer. 
 
     
     
       7. A method of manufacturing an array substrate, comprising following steps:
 a barrier layer forming step, comprising defining a display area and a bending area of an array substrate to be manufactured, providing a substrate, and forming a barrier layer on the substrate; 
 an insulating layer forming step, comprising forming an insulating layer on the barrier layer; 
 a conductive layer forming step, comprising disposing a plurality of conductive layers spaced apart from each other in the insulating layer; 
 an interlayer insulating layer forming step, comprising forming an interlayer insulating layer on the conductive layers, wherein a depressed surface of the interlayer insulating layer away from the substrate reaches the barrier layer to form a recess; and 
 an organic layer forming step, coating the organic material on the interlayer insulating layer and in the recess, and removing a portion of the organic material in the recess by using a halftone mask; 
 wherein a surface of the organic layer away from the substrate aligns with a surface of the interlayer insulating layer away from the substrate. 
 
     
     
       8. The method of  claim 7 , further comprising following steps:
 a buffer layer forming step, comprising forming a buffer layer between the barrier layer and the insulating layer, wherein the organic layer penetrates through the buffer layer; 
 an active layer forming step, comprising forming an active layer between the buffer layer and the insulating layer; 
 a source/drain layer forming step, comprising forming a source/drain layer on the interlayer insulating layer, and connecting the source/drain layer to the active layer by a through hole; and 
 a planarization layer forming step, comprising forming a planarization layer on the source/drain layer. 
 
     
     
       9. The method of  claim 7 , wherein the insulating layer forming step comprises a first gate insulating layer forming step and a second gate insulating layer forming step, and the conductive layer forming step comprises a first gate layer forming step and a second gate layer forming step;
 the first gate insulating layer forming step comprises forming a first gate insulating layer on the barrier layer; 
 the first gate layer forming step comprises forming a first gate layer on the first gate insulating layer; 
 the second gate insulating layer forming step comprises forming a second gate insulating layer on the first gate layer; and 
 the second gate layer forming step comprises forming a second gate layer on the second gate insulating layer; 
 wherein the interlayer insulating layer is formed on the second gate layer. 
 
     
     
       10. The method of  claim 7 , wherein the organic layer forming step further comprises removing the organic material on the insulating layer by exposure, wherein the surface of the organic layer away from the substrate aligns with the surface of the interlayer insulating layer away from the substrate after the organic layer forming step. 
     
     
       11. The method of  claim 7 , wherein a light transmittance of the halftone mask ranges from 20% to 45%.