Systems and methods for performing a write pattern in memory devices

Abstract

A semiconductor device may include a memory bank and a plurality of mode registers that communicatively couple to each of the plurality of memory banks. The plurality of mode registers may include a pattern of data stored therein. The semiconductor device may also include a bank control that receives a write pattern command that causes the bank control to write the pattern of data into the memory bank, send a signal to a multiplexer to couple the plurality of mode registers to the memory bank, and write the pattern of data to the memory bank via the plurality of mode registers.

What is claimed is: 
     
       1. A semiconductor device, comprising:
 a plurality of memory banks; 
 a plurality of mode registers configured to communicatively couple to each of the plurality of memory banks, wherein the plurality of mode registers comprise a pattern of data stored therein; and 
 a bank control configured to:
 generate an error correction code from the pattern of data; 
 store the error correction code associated with the pattern of data in the bank control; 
 receive a write pattern command configured to cause the bank control to write the pattern of data into a memory bank of the plurality of memory banks; 
 send a signal to a multiplexer to couple the plurality of mode registers to the memory bank of the plurality of memory banks; and 
 write an error-corrected pattern of data to the memory bank of the plurality of memory banks via the plurality of mode registers, utilizing the stored error correction code. 
 
 
     
     
       2. The semiconductor device of  claim 1 , wherein the multiplexer is configured to communicatively couple the plurality of mode registers or couple one or more DQ inputs to the memory bank. 
     
     
       3. The semiconductor device of  claim 1 , wherein the bank control is configured to:
 receive the pattern of data prior to receiving the write pattern command; 
 generate the error correction code based on the pattern of data; and 
 write the error-corrected pattern of data from the plurality of mode registers. 
 
     
     
       4. The semiconductor device of  claim 1 , wherein the error correction code comprises one or more parity bits. 
     
     
       5. The semiconductor device of  claim 1 , comprising a latch circuit coupled to the plurality of mode registers, wherein the bank control is configured to store error correction code in the latch circuit. 
     
     
       6. The semiconductor device of  claim 1 , comprising internal registers coupled to the plurality of mode registers, wherein the bank control is configured to store error correction code in the internal registers. 
     
     
       7. The semiconductor device of  claim 1 , wherein the bank control is configured to store error correction code in the internal registers. 
     
     
       8. The semiconductor device of  claim 1 , wherein the bank control is configured to:
 receive the pattern of data as a plurality of sets of parallel data prior to receiving the write pattern command; and 
 generate the error-corrected pattern of data based on the plurality of sets of parallel data. 
 
     
     
       9. The semiconductor device of  claim 8 , comprising a deserializer component configured to provide the pattern of data as the plurality of sets of parallel data. 
     
     
       10. The semiconductor device of  claim 8 , wherein each respective set of the plurality of sets of parallel data is written into a respective one of the plurality of mode registers. 
     
     
       11. The semiconductor device of  claim 8 , wherein each respective set of the plurality of sets comprises either a plurality of zero values or a plurality of one values. 
     
     
       12. The semiconductor device of  claim 1 , comprising a deserializer component configured to:
 receive the pattern of data as serial data to be written into the plurality of mode registers; 
 convert the serial data into a parallel dataset; and 
 transmit a respective portion of the parallel dataset to a respective one of the plurality of mode registers. 
 
     
     
       13. The semiconductor device of  claim 1 , wherein the write pattern command is configured to cause the bank control to write the pattern of data into the memory bank a plurality of times. 
     
     
       14. The semiconductor device of  claim 1 , wherein the number of mode registers of the plurality of mode registers is equal to a number of DQ inputs received via an input/output interface of the semiconductor device.