Low-power digital signal processing

Abstract

Systems and devices are provided to perform low-power digital filtering of sensor or other data based on bitwise operations. A reference sinusoid is encoded via a plurality of pulse trains, such that each pulse train includes a number of pulses n representing a value of the reference sinusoid out of a maximum possible pulses corresponding to an encoding quantization level. A circular register stores a representation of the encoded sinusoid. A set of multiple logical gate blocks are configured to multiply, via one or more bitwise operations, each of multiple bits of a received input signal with a pulse train corresponding to a value of the encoded sinusoid. A logic circuit coupled to the circular register and the set of multiple logical gate blocks is configured to generate, based on the encoded sinusoid and on the input signal, an output signal indicating an approximate value of the received input signal multiplied by the encoded sinusoid.

What is claimed is: 
     
       1. A circuit, comprising:
 a circular register configured to store a representation of a first encoded sinusoid; 
 a set of multiple logical gate blocks that are each configured to multiply, via one or more bitwise operations, each of multiple bits of a received input signal with a pulse train corresponding to a value of the first encoded sinusoid; and 
 a logic circuit coupled to the circular register and the set of multiple logical gate blocks, the logic circuit configured to generate, based on the first encoded sinusoid and on the input signal, an output signal indicating an approximate value of the received input signal multiplied by the first encoded sinusoid. 
 
     
     
       2. The circuit of  claim 1 , wherein the representation of the first encoded sinusoid is a quantized representation of a first reference sinusoid encoded via a plurality of pulse trains, wherein each pulse train includes a number of pulses n representing a value of the first reference sinusoid at time t out of a maximum possible pulses m, and wherein m represents a quantization level of the first encoded sinusoid. 
     
     
       3. The circuit of  claim 1 , wherein the logic circuit comprises an integrator that is configured to provide an output of the circuit comprising integrated results of the multiple logical gate blocks over time. 
     
     
       4. The circuit of  claim 1 , comprising a second set of multiple logical gate blocks that are each configured to multiply, via one or more bitwise operations, the respective one of the multiple bits of the received input signal with a second pulse train corresponding to a value of a second encoded sinusoid, the second encoded sinusoid having a same frequency as the first encoded sinusoid and being out of phase with the first encoded sinusoid. 
     
     
       5. The circuit of  claim 4 , wherein the second encoded sinusoid is 90° out of phase with the first encoded sinusoid. 
     
     
       6. The circuit of  claim 1 , comprising a sign control block to provide one or more control signals to the set of multiple logical gate blocks based at least in part on a sign of the received input signal and on a sign of the first encoded sinusoid. 
     
     
       7. The circuit of  claim 1 , wherein in operation, each of the multiple logical gate blocks at least:
 receives a first clock signal, a respective bit of the received input signal, the pulse train corresponding to a value of the first encoded sinusoid, and a first pair of control signals that are related to a sign of the received input signal and to a sign of the first encoded sinusoid; 
 provides a second clock signal based on the first clock signal, on the respective bit of the received input signal, and on the pulse train corresponding to a value of the first encoded sinusoid; and 
 provides a second pair of control signals based on a logical comparison of the first pair of control signals. 
 
     
     
       8. A device, comprising:
 one or more sensors that, in operation, generate a multi-bit sensor signal; 
 one or more processors; and 
 frequency analysis circuitry communicatively coupled to the one or more sensors and to the one or more processors, the frequency analysis circuitry including:
 a circular register configured to store a representation of a first encoded sinusoid; 
 a set of multiple logical gate blocks that are each configured to multiply, via one or more bitwise operations, each of multiple bits of the multi-bit sensor signal with a pulse train corresponding to a value of the first encoded sinusoid; and 
 a logic circuit coupled to the circular register and the set of multiple logical gate blocks, the logic circuit configured to generate, based on the first encoded sinusoid and on the multi-bit sensor signal, an output signal indicating an approximate value of the received input signal multiplied by the first encoded sinusoid. 
 
 
     
     
       9. The device of  claim 8 , wherein the representation of the first encoded sinusoid is a quantized representation of a first reference sinusoid encoded via a plurality of pulse trains, wherein each pulse train includes a number of pulses n representing a value of the first reference sinusoid at time t out of a maximum possible pulses m, and wherein m represents a quantization level of the first encoded sinusoid. 
     
     
       10. The device of  claim 8 , wherein the logic circuit comprises an integrator that is configured to provide an output of the circuit comprising integrated results of the multiple logical gate blocks over time. 
     
     
       11. The device of  claim 8 , comprising a second set of multiple logical gate blocks that are each configured to multiply, via one or more bitwise operations, the respective one of the multiple bits of the multi-bit sensor signal with a second pulse train corresponding to a value of a second encoded sinusoid, the second encoded sinusoid having a same frequency as the first encoded sinusoid and being out of phase with the first encoded sinusoid. 
     
     
       12. The circuit of  claim 11 , wherein the second encoded sinusoid is 90° out of phase with the first encoded sinusoid. 
     
     
       13. The device of  claim 8 , comprising a sign control block to provide one or more control signals to the set of multiple logical gate blocks based at least in part on a sign of the multi-bit sensor signal and on a sign of the first encoded sinusoid. 
     
     
       14. The device of  claim 8 , wherein in operation, each of the multiple logical gate blocks at least:
 receives a first clock signal, a respective bit of the multi-bit sensor signal, the pulse train corresponding to a value of the first encoded sinusoid, and a first pair of control signals that are related to a sign of the multi-bit sensor signal and to a sign of the first encoded sinusoid; 
 provides a second clock signal based at least in part on the first clock signal, on the respective bit of the multi-bit sensor signal, and on the pulse train corresponding to a value of the first encoded sinusoid; and 
 provides a second pair of control signals based at least in part on a logical comparison of the first pair of control signals. 
 
     
     
       15. A method, comprising:
 storing a representation of a first encoded sinusoid in a first circular register; 
 multiplying, via one or more bitwise operations, each of multiple bits of a received input signal with a pulse train corresponding to a value of the first encoded sinusoid; and 
 generating, based on the first encoded sinusoid and on the received input signal, an output signal indicating an approximate value of the received input signal multiplied by the first encoded sinusoid. 
 
     
     
       16. The method of  claim 15 , wherein multiplying each of the multiple bits of the received input signal with the pulse train corresponding to a value of the first encoded sinusoid includes multiplying a respective bit of the received input signal at time t with a pulse train comprising a number of pulses n representing a value of a first reference sinusoid at time t out of a maximum possible pulses m, the maximum possible pulses m representing a quantization level of the first encoded sinusoid. 
     
     
       17. The method of  claim 15 , wherein generating the output signal based on the first encoded sinusoid and on the received input signal includes generating integrated results of multiplying each of the multiple bits of the received input signal with the pulse train corresponding to a value of the first encoded sinusoid over time. 
     
     
       18. The method of  claim 15 , comprising multiplying, via one or more bitwise operations, a respective bit of the received input signal with a second pulse train corresponding to a value of a second encoded sinusoid, the second encoded sinusoid having a same frequency as the first encoded sinusoid and being out of phase with the first encoded sinusoid. 
     
     
       19. The method of  claim 18 , wherein the second encoded sinusoid is 90° out of phase with the first encoded sinusoid. 
     
     
       20. The method of  claim 15 , wherein multiplying each of the multiple bits of the received input signal with a pulse train corresponding to a value of the first encoded sinusoid includes providing one or more control signals based at least in part on a sign of the received input signal and on a sign of the first encoded sinusoid.