Semiconductor memory device and method of operating the semiconductor memory device

Abstract

Provided herein is a semiconductor memory device and a method of operating the semiconductor memory device. The semiconductor memory device includes: a memory cell array including a plurality of word lines; a peripheral circuit coupled to the memory cell array through the plurality of word lines and configured to apply a program voltage to a selected word line of the plurality of word lines during a program operation and apply a pass voltage to unselected word lines of the plurality of word lines; and control logic configured to control the peripheral circuit to apply a first pass voltage to word lines adjacent to the selected word line among the unselected word lines during a first program operation of the program operation and apply a second pass voltage to the word lines adjacent to the selected word line during a second program operation of the program operation.

What is claimed is: 
     
       1. A semiconductor memory device comprising:
 a memory cell array including a plurality of word lines; 
 a peripheral circuit coupled to the memory cell array through the plurality of word lines and configured to apply a program voltage to a selected word line of the plurality of word lines during a program operation and apply a pass voltage to unselected word lines of the plurality of word lines; and 
 control logic configured to control the peripheral circuit to apply a first pass voltage to word lines adjacent to the selected word line among the unselected word lines during a first program operation of the program operation and apply a second pass voltage to the word lines adjacent to the selected word line during a second program operation of the program operation, 
 wherein, during the program operation, the first program operation is performed on at least one first page corresponding to a word line which is currently selected and after the first program operation on the at least one first page is completed, the second program operation is performed on at least one second page corresponding to a word line which is previously selected. 
 
     
     
       2. The semiconductor memory device according to  claim 1 , wherein the first pass voltage is greater than the second pass voltage. 
     
     
       3. The semiconductor memory device according to  claim 1 , wherein the control logic sets a program voltage application time of the first program operation and a program voltage application time of the second program operation such that the program voltage application time of the first program operation is longer than the program voltage application time of the second program operation. 
     
     
       4. The semiconductor memory device according to  claim 1 , wherein the first program operation is a foggy program operation, and the foggy program operation is an operation of programming threshold voltages of memory cells included in the memory cell array to values equal to or greater than a pre-threshold voltage less than a target threshold voltage. 
     
     
       5. The semiconductor memory device according to  claim 4 , wherein the second program operation is a fine program operation, and the fine program operation is an operation of programming the threshold voltages of the memory cells to values equal to or greater than the target threshold voltage. 
     
     
       6. A semiconductor memory device comprising:
 a memory cell array including a plurality of word lines; 
 a peripheral circuit coupled to the memory cell array through the plurality of word lines and configured to apply a program voltage to a selected word line of the plurality of word lines during a program operation and apply a pass voltage to unselected word lines of the plurality of word lines; and 
 control logic configured to control the peripheral circuit to perform a program voltage application operation of applying the program voltage and the pass voltage to the plurality of word lines for a first time during a first program operation of the program operation and perform the program voltage application operation for a second time during a second program operation of the program operation, 
 wherein, during the program operation, the first program operation is performed on at least one first page corresponding to a word line which is currently selected and after the first program operation on the at least one first page is completed, the second program operation is performed on at least one second page corresponding to a word line which is previously selected. 
 
     
     
       7. The semiconductor memory device according to  claim 6 , wherein the first time is greater than the second time. 
     
     
       8. The semiconductor memory device according to  claim 6 , wherein the control logic controls the peripheral circuit to apply a first pass voltage to word lines adjacent to the selected word line among the unselected word lines during the program voltage application of the first program operation, and apply a second pass voltage to remaining unselected word lines among the unselected word lines. 
     
     
       9. The semiconductor memory device according to  claim 8 ,
 wherein the control logic controls the peripheral circuit to apply a third pass voltage to the word lines adjacent to the selected word line during the program voltage application operation of the second program operation, and apply the second pass voltage to the remaining unselected word lines, and 
 wherein the first pass voltage is greater than the third pass voltage. 
 
     
     
       10. The semiconductor memory device according to  claim 6 , wherein the first program operation is a foggy program operation, and the foggy program operation is an operation of programming threshold voltages of memory cells included in the memory cell array to values equal to or greater than a pre-threshold voltage less than a target threshold voltage. 
     
     
       11. The semiconductor memory device according to  claim 10 , wherein the second program operation is a fine program operation, and the fine program operation is an operation of programming the threshold voltages of the memory cells to values equal to or greater than the target threshold voltage. 
     
     
       12. A method of operating a semiconductor memory device, comprising:
 performing a first program operation by applying a program voltage to a first selected word line and applying a first pass voltage to word lines adjacent to the first selected word line; 
 performing the first program operation by applying the program voltage to a second selected word line and applying the first pass voltage to word lines adjacent to the second selected word line; and 
 performing a second program operation by applying the program voltage to the first selected word line and applying a second pass voltage less than the first pass voltage to the word lines adjacent to the first selected word line. 
 
     
     
       13. The method according to  claim 12 , wherein the first program operation is a foggy program operation, and the second program operation is a fine program operation. 
     
     
       14. The method according to  claim 12 ,
 wherein the first program operation includes first to m-th program loops (m is a positive integer) among a plurality of program loops included in a program operation using an incremental step pulse program (ISPP) scheme, and 
 wherein the second program operation includes m+1-th to last program loops among the plurality of program loops. 
 
     
     
       15. The method according to  claim 12 , wherein a program voltage application period of the first program operation is greater than a program voltage application period of the second program operation.