Signal processing bias circuit for microphone

Abstract

A bias circuit includes a digital-to-analog converter configured to receive a digital input and output an analog signal; an integrator coupled to a first node that is coupled to the digital-to-analog converter and an amplifier, and coupled to a second node that is coupled to a positive input port of a first comparator and a negative input port of a second comparator; the digital signal processor coupled to an output port of the first comparator and an output port of the second comparator, and coupled to an input port of the digital-to-analog converter.

What is claimed is: 
     
       1. A bias circuit, comprising:
 a digital-to-analog converter configured to receive a digital input and output an analog signal; 
 first and second comparators; 
 an integrator coupled to a first node that is coupled to the digital-to-analog converter and an amplifier, and coupled to a second node that is coupled to a positive input port of the first comparator and a negative input port of the second comparator; 
 the positive input port of the first comparator is coupled to the second node, a negative input port of the first comparator is coupled to a reference voltage generator, and an output port of the first comparator is coupled to a digital signal processor; 
 a positive input port of the second comparator is coupled to the reference voltage generator, the negative input port of the second comparator is coupled to the second node, and an output port of the second comparator is coupled to the digital signal processor; and 
 the digital signal processor coupled to the output port of the first comparator and the output port of the second comparator, and coupled to an input port of the digital-to-analog converter. 
 
     
     
       2. The bias circuit in  claim 1 , wherein the digital signal processor repeatedly generates a different digital signal based on a first decision result of the first comparator and a second decision result of the second comparator, wherein the digital signal processor ceases generating the different digital signal when both the first and second decision results are logic low. 
     
     
       3. The bias circuit in  claim 1 , wherein the integrator comprises
 a second operational amplifier wherein a positive input port of the second operational amplifier is coupled to a voltage of common mode; and 
 an adjustable second resistor coupled to an output port of the second operational amplifier and the first node, a first capacitor coupled between the output port of the second operational amplifier and a negative input port of the second operational amplifier, and a first resistor coupled to the negative input port of the second operational amplifier. 
 
     
     
       4. The bias circuit in  claim 1 , wherein the first node is coupled to an output port of the digital-to-analog converter that is coupled to a microphone. 
     
     
       5. The bias circuit in  claim 1 , wherein the digital-to-analog converter is an 8-bit current output digital-to-analog converter. 
     
     
       6. A circuit comprising:
 a digital-to-analog converter configured to receive a digital input and output an analog signal; 
 an amplifier comprising a first operational amplifier and an adjustable reference resistor coupled between a negative input port of the first operational amplifier and an output port of the first operational amplifier; 
 an analog-to-digital converter coupled between the output port of the first operational amplifier and a digital signal processor; 
 first and second comparators; 
 an integrator coupled to a first node that is coupled to the digital-to-analog converter and an amplifier, and coupled to a second node that is coupled to a positive input port of the first comparator and a negative input port of the second comparator; 
 the positive input port of the first comparator is coupled to the second node, a negative input port of the first comparator is coupled to a reference voltage generator, and an output port of the first comparator is coupled to the digital signal processor; 
 a positive input port of the second comparator is coupled to the reference voltage generator, the negative input port of the second comparator is coupled to the second node, and an output port of the second comparator is coupled to the digital signal processor; and 
 the digital signal processor coupled to the output port of the first comparator, the output port of the second comparator and the analog-to-digital converter, and coupled to an input port of the digital-to-analog converter. 
 
     
     
       7. The circuit in  claim 6 , wherein the digital signal processor repeatedly generates a different digital signal based on a first decision result of the first comparator and a second decision result of the second comparator, wherein the digital signal processor ceases generating the different digital signal when both the first and second decision results are logic low. 
     
     
       8. The circuit in  claim 6 , wherein the integrator comprises:
 a second operational amplifier wherein a positive input port of the second operational amplifier is coupled to a voltage of common mode; and 
 an adjustable second resistor coupled to an output port of the second operational amplifier and the first node, a first capacitor coupled between the output port of the second operational amplifier and a negative input port of the second operational amplifier, and a first resistor coupled to the negative input port of the second operational amplifier. 
 
     
     
       9. The circuit in  claim 6 , wherein the first node is coupled to an output port of the digital-to-analog converter that is coupled to a microphone. 
     
     
       10. The circuit in  claim 6 , wherein the digital-to-analog converter is an 8-bit current output digital-to-analog converter. 
     
     
       11. A method of generating an analog signal with a bias circuit, comprising:
 generating, by a digital-to-analog converter, an analog signal; 
 generating, by an amplifier, a first voltage at an output port of a first operational amplifier; 
 generating, by an integrator, a second voltage result by comparing a reversed first voltage at a negative input port of a second operational amplifier and a voltage of common mode at a positive input port of the second operational amplifier; 
 comparing, by a first comparator, the second voltage and a first reference voltage; 
 comparing, by a second comparator, the second voltage and a second reference voltage; 
 generating, by a digital signal processor, a digital signal result by processing a first decision result of the first comparator and a second decision result of the second comparator; 
 generating, by the digital signal processor, a digital signal at an input port of the digital-to-analog converter; and 
 generating, by the digital-to-analog converter, the analog signal at a negative input port of the first operational amplifier. 
 
     
     
       12. The method of generating the analog signal with the bias circuit in  claim 11 , further comprising repeatedly generating, with the digital signal processor, a different digital signal based on the first decision result of the first comparator and the second decision result of the second comparator, wherein the digital signal processor ceases generating the different digital signal when both the first and second decision results are logic low. 
     
     
       13. The method of generating the analog signal with the bias circuit in  claim 11 , wherein
 the integrator coupled to a first node that is coupled to the digital-to-analog converter and the amplifier, and coupled to a second node that is coupled to a positive input port of the first comparator and a negative input port of the second comparator; 
 the first comparator, wherein the positive input port of the first comparator is coupled to the second node, a negative input port of the first comparator is coupled to a reference voltage generator, and an output port of the first comparator is coupled to the digital signal processor; 
 the second comparator, wherein a positive input port of the second comparator is coupled to the reference voltage generator, the negative input port of the second comparator is coupled to the second node, and an output port of the second comparator is coupled to the digital signal processor; and 
 the digital signal processor coupled to the output port of the first comparator and the output port of the second comparator, and coupled to the input port of the digital-to-analog converter. 
 
     
     
       14. The method of generating the analog signal with the bias circuit in  claim 11 , wherein the integrator comprises
 the second operational amplifier wherein the positive input port is coupled to the voltage of common mode; 
 an adjustable second resistor coupled to the output port of the second operational amplifier and the first node, a first capacitor coupled between the output port of the second operational amplifier and the negative input port of the second operational amplifier, and a first resistor coupled to the negative input port of the second operational amplifier. 
 
     
     
       15. The method of generating the analog signal with the bias circuit in  claim 11 , wherein the first node is coupled to the output port of the digital-to-analog converter that is coupled to a microphone. 
     
     
       16. The method of generating the analog signal with the bias circuit in  claim 15 , further comprising providing the analog signal to the microphone. 
     
     
       17. The method of generating the analog signal with the bias circuit in  claim 11 , wherein the digital-to-analog converter is an 8-bit current output digital-to-analog converter. 
     
     
       18. The method of generating the analog signal with the bias circuit in  claim 11 , wherein the bias circuit resides in an integrated circuit. 
     
     
       19. The method of generating the analog signal with the bias circuit in  claim 11 , wherein the first reference voltage is higher than the second reference voltage.