High linearity low noise amplifier

Abstract

An amplifier circuit is disclosed. The amplifier circuit includes an input terminal configured to receive an input signal, an output terminal configured to transmit an output signal, and a first signal path including a first amplifying circuit, where the first amplifying circuit is configured to receive the input signal and to transmit a first amplified output to the output terminal, and where the first amplified output includes first amplifier circuit harmonic noise. The amplifier circuit also includes a second signal path including a second amplifying circuit, where the second amplifying circuit receives the input signal and transmits a second amplified output to the output terminal, and where the second amplified output includes second amplifier circuit harmonic noise. The output signal includes the first and second amplified outputs, and the first amplifying circuit harmonic noise is at least partially canceled by the second amplifying circuit harmonic noise in the output signal.

What is claimed is: 
     
       1. An amplifier circuit, comprising:
 an input terminal configured to receive an input signal; 
 an output terminal configured to transmit an output signal; 
 a first signal path comprising a first amplifying circuit, wherein the first amplifying circuit is configured to receive the input signal via a first inverter input and to transmit a first amplified output via a first inverter output to the output terminal, a first feedback component is coupled between the first inverter input and the first inverter output, and the first amplified output includes first amplifier circuit harmonic noise; and 
 a second signal path comprising a second amplifying circuit, wherein the second amplifying circuit is configured to receive the input signal via a second inverter input and to transmit a second amplified output via a second inverter output to the output terminal, a second feedback component is coupled between the second inverter input and the second inverter output, and the second amplified output includes second amplifier circuit harmonic noise, 
 wherein the output signal comprises the first and second amplified outputs, and wherein the first amplifying circuit harmonic noise is at least partially canceled by the second amplifying circuit harmonic noise in the output signal. 
 
     
     
       2. The amplifier circuit of  claim 1 , further comprising an input capacitor, configured to couple the input signal to each of the first and second signal paths. 
     
     
       3. The amplifier circuit of  claim 1 , further comprising an input capacitor, configured to couple the input signal to each of the first and second amplifying circuits. 
     
     
       4. The amplifier circuit of  claim 1 , wherein:
 one or more first PMOS devices connected to the first inverter output; and 
 one or more first NMOS devices connected to the first inverter output; 
 one or more second PMOS devices connected to the second inverter output; 
 one or more second NMOS devices connected to the second inverter output; 
 a transconductance per width of the first PMOS devices is different from a transconductance per width of the second PMOS devices; and 
 a transconductance per width of the first NMOS devices is different from a transconductance per width of the second NMOS devices. 
 
     
     
       5. The amplifier circuit of  claim 1 , wherein:
 one or more first PMOS devices connected to the first inverter output; and 
 one or more first NMOS devices connected to the first inverter output; 
 one or more second PMOS devices connected to the second inverter output; 
 one or more second NMOS devices connected to the second inverter output; 
 a voltage difference between the drain and source of the first PMOS devices is different from a voltage difference between the drain and source of the second PMOS devices; and 
 a voltage difference between the drain and source of the first NMOS devices is different from a voltage difference between the drain and source of the second NMOS devices. 
 
     
     
       6. The amplifier circuit of  claim 1 , wherein:
 the first signal path comprises a first output capacitor, wherein the first output capacitor is configured to couple the first amplified output to the output terminal; and 
 the second signal path comprises a second output capacitor, wherein the second output capacitor is configured to couple the second amplified output to the output terminal. 
 
     
     
       7. A method of using an amplifier circuit, the method comprising:
 with a first inverter input of a first amplifying circuit of a first signal path, receiving an input signal; 
 with a first inverter output of the first amplifying circuit, transmitting a first amplified output to an output terminal, wherein a first feedback component is coupled between the first inverter input and the first inverter output, and the first amplified output includes first amplifier circuit harmonic noise; 
 with a second inverter input of a second amplifying circuit of a second signal path, receiving the input signal; 
 with a second inverter output of the second amplifying circuit, transmitting a second amplified output to the output terminal, wherein a second feedback component is coupled between the second inverter input and the second inverter output, and the second amplified output includes second amplifier circuit harmonic noise; 
 wherein the output signal comprises the first and second amplified outputs, and wherein the first amplifying circuit harmonic noise is at least partially canceled by the second amplifying circuit harmonic noise in the output signal. 
 
     
     
       8. The method of  claim 7 , further comprising, with an input capacitor, coupling the input signal to each of the first and second signal paths. 
     
     
       9. The method of  claim 7 , further comprising, with an input capacitor, coupling the input signal to each of the first and second amplifying circuits. 
     
     
       10. The method of  claim 7 , wherein:
 one or more first PMOS devices is connected to the first inverter output; 
 one or more first NMOS devices is connected to the first inverter output; 
 one or more second PMOS devices is connected to the second inverter output; 
 one or more second NMOS devices is connected to the second inverter output; 
 a transconductance per width of the first PMOS devices is different from a transconductance per width of the second PMOS devices; and 
 a transconductance per width of the first NMOS devices is different from a transconductance per width of the second NMOS devices. 
 
     
     
       11. The method of  claim 7 , wherein:
 one or more first PMOS devices connected to the first inverter output; 
 one or more first NMOS devices connected to the first inverter output; 
 one or more second PMOS devices connected to the second inverter output; 
 one or more second NMOS devices connected to the second inverter output; 
 a voltage difference between the drain and source of the first PMOS devices is different from a voltage difference between the drain and source of the second PMOS devices; and 
 a voltage difference between the drain and source of the first NMOS devices is different from a voltage difference between the drain and source of the second NMOS devices. 
 
     
     
       12. The method of  claim 7 , further comprising:
 with a first output capacitor of the first signal path, coupling the first amplified output to the output terminal; and 
 with a second output capacitor of the second signal path, coupling the second amplified output to the output terminal. 
 
     
     
       13. A receiver circuit, comprising:
 a low noise amplifier circuit (LNA), comprising:
 an input terminal configured to receive an input signal, 
 an output terminal configured to transmit an output signal, 
 a first signal path comprising a first amplifying circuit, wherein the first amplifying circuit is configured to receive the input signal via a first inverter input and to transmit a first amplified output via a first inverter output to the output terminal, a first feedback component is coupled between the first inverter input and the first inverter output, and the first amplified output includes first amplifier circuit harmonic noise, 
 a second signal path comprising a second amplifying circuit, wherein the second amplifying circuit is configured to receive the input signal via a second inverter input and to transmit a second amplified output via a second inverter output to the output terminal, a second feedback component is coupled between the second inverter input and the second inverter output, and the second amplified output includes second amplifier circuit harmonic noise, 
 wherein the output signal comprises the first and second amplified outputs, and wherein the first amplifying circuit harmonic noise is at least partially canceled by the second amplifying circuit harmonic noise in the output signal; 
 
 an analog-to-digital converter (ADC) configured to receive an analog signal based on the output signal of the LNA, and to generate a digital signal based on the received analog signal; and
 a controller, configured to receive the digital signal. 
 
 
     
     
       14. The receiver of  claim 13 , wherein:
 one or more first PMOS devices connected to the first inverter output; 
 one or more first NMOS devices connected to the first inverter output; 
 one or more second PMOS devices connected to the second inverter output; 
 one or more second NMOS devices connected to the second inverter output; 
 a transconductance per width of the first PMOS devices is different from a transconductance per width of the second PMOS devices; and 
 a transconductance per width of the first NMOS devices is different from a transconductance per width of the second NMOS devices. 
 
     
     
       15. The receiver of  claim 13 , wherein:
 one or more first PMOS devices connected to the first inverter output; 
 one or more first NMOS devices connected to the first inverter output; 
 one or more second PMOS devices connected to the second inverter output; 
 one or more second NMOS devices connected to the second inverter output; 
 a voltage difference between the drain and source of the first PMOS devices is different from a voltage difference between the drain and source of the second PMOS devices; and 
 a voltage difference between the drain and source of the first NMOS devices is different from a voltage difference between the drain and source of the second NMOS devices.