Semiconductor package

Abstract

A transistor ( 2 ) and a matching circuit substrate ( 3 - 6 ) are provided on a base plate ( 1 ) and connected to each other. A frame ( 15 ) is provided on the base plate ( 1 ) and surrounds the transistor ( 2 ) and the matching circuit substrate ( 3 - 6 ). The frame ( 15 ) has a smaller linear expansion coefficient than that of the base plate ( 1 ). A screwing portion ( 17 ) is provided in the frame ( 15 ). A size of the base plate ( 1 ) is smaller than that of the frame ( 15 ).

The invention claimed is: 
     
       1. A semiconductor package comprising:
 a base plate; 
 a transistor and a matching circuit substrate which are provided on the base plate and connected to each other; and 
 a frame provided on the base plate and surrounding the transistor and the matching circuit substrate, 
 wherein the frame is a single integral piece and has a smaller linear expansion coefficient than that of the base plate, 
 a screwing portion is provided in the frame, and 
 a size of the base plate is smaller than that of the frame. 
 
     
     
       2. The semiconductor package according to  claim 1 , wherein
 the screwing portion is provided in the frame such that a screw passing through the screwing portion to threadedly secure the semiconductor package directly engages with an upper surface of the frame so as to provide a downward force on the upper surface of the frame. 
 
     
     
       3. The semiconductor package according to  claim 1 , wherein
 the screwing portion provided in the frame is spaced from the base plate in a plan view. 
 
     
     
       4. The semiconductor package according to  claim 1 , wherein
 the transistor is provided on an upper surface of the base plate, and 
 the screwing portion provided in the frame is positioned above the base plate. 
 
     
     
       5. The semiconductor package according to  claim 1 , wherein
 the transistor and the matching circuit substrate are provided on a largest surface of the base plate, and 
 the frame is provided on the largest surface. 
 
     
     
       6. The semiconductor package according to  claim 1 , wherein
 the transistor and the matching circuit substrate are provided on an upper surface of the base plate, and 
 the frame surrounds the transistor and the matching circuit substrate in a plane parallel with a plane of the upper surface.