Memory system

Abstract

A memory system includes a nonvolatile memory and a controller that performs first, second, and third processes on memory cells of the nonvolatile memory. The first process is performed on first memory cells to store a first value therein, such that a highest threshold voltage among the threshold voltages of the first memory cells is set as a first threshold voltage. The second process is performed on second memory cells to store a second value therein, such that a lowest threshold voltage among the threshold voltages of the second memory cells is set as a second threshold voltage higher than the first threshold voltage. The third process performed on third memory cells such that a lowest threshold voltage in the third memory cells is lower than the first threshold voltage, and a highest threshold voltage in the third memory cells is higher than the second threshold voltage.

What is claimed is: 
     
       1. A memory system comprising:
 a nonvolatile memory including a first storage area and a second storage area each including a plurality of memory cells; and 
 a controller configured to perform a first process on a plurality of first memory cells provided in the first storage area, a second process on a plurality of second memory cells provided in the first storage area, and in response to a request for a random number, a third process on a plurality of third memory cells provided in the second storage area, wherein 
 each of the plurality of memory cells stores a plurality of values according to a threshold voltage, the plurality of values including at least a first value and a second value, the second value being adjacent to the first value in relation to the threshold voltage, 
 the first process is a process of storing the first value in the plurality of first memory cells and setting a highest threshold voltage among the threshold voltages of the plurality of first memory cells as a first threshold voltage, 
 the second process is a process of storing the second value in the plurality of second memory cells and setting a lowest threshold voltage among the threshold voltages of the plurality of second memory cells as a second threshold voltage that is higher than the first threshold voltage, and 
 the third process is a process in which a lowest threshold voltage among the threshold voltages of the plurality of third memory cells is made lower than the first threshold voltage, and a highest threshold voltage among the threshold voltages of the plurality of third memory cells is made higher than the second threshold voltage. 
 
     
     
       2. The memory system according to  claim 1 , wherein
 the controller is configured to use a result read from the second storage area in a read operation using a read level that is higher than the first threshold voltage and lower than the second threshold voltage as the random number. 
 
     
     
       3. The memory system according to  claim 2 , wherein
 the controller is configured to set as the read level a central voltage of a threshold voltage distribution of the plurality of third memory cells. 
 
     
     
       4. The memory system according to  claim 2 , wherein
 the controller is configured to generate key information for encrypting data to be written into the nonvolatile memory by using the result read from the second storage area in the read operation using the read level. 
 
     
     
       5. The memory system according to  claim 2 , wherein
 the controller is configured to generate a timing for reading data from the nonvolatile memory by using the result read from the second storage area in the read operation using the read level. 
 
     
     
       6. The memory system according to  claim 1 , wherein
 a threshold voltage distribution width of the plurality of third memory cells is wider than a threshold voltage distribution width of the plurality of second memory cells. 
 
     
     
       7. The memory system according to  claim 1 , wherein
 the first process is an erase process performed on the plurality of first memory cells. 
 
     
     
       8. A memory system comprising:
 a nonvolatile memory including a plurality of memory cells; and 
 a controller configured to generate a random number by performing: 
 a rough write operation on the plurality of memory cells; and 
 a read operation on the plurality of memory cells after the rough write operation, 
 wherein a read voltage that is applied during the read operation is set to be higher than a lowest voltage of threshold voltages of the plurality of memory cells on which the rough write operation has been performed by substantially one-half of a width of a range of the threshold voltages of the plurality of memory cells on which the rough write operation has been performed. 
 
     
     
       9. The memory system according to  claim 8 , wherein no other write operation is performed on the plurality of memory cells after the rough write operation before the read operation. 
     
     
       10. The memory system according to  claim 9 , wherein the controller is configured to output results of the read operation as the random number. 
     
     
       11. The memory system according to  claim 9 , wherein the controller is configured to perform one or more additional read operations after the rough write operation and outputs combined results of the read operations as the random number. 
     
     
       12. The memory system according to  claim 8 , wherein during the rough write operation, threshold voltages of the plurality of memory cells are changed to a target threshold voltage level without performing any verification against the target threshold voltage level. 
     
     
       13. A method of operating a memory system using a random number, the memory system comprising a nonvolatile memory including a first storage area and a second storage area, each including a plurality of memory cells, said method comprising:
 performing a first process on a plurality of first memory cells provided in the first storage area, a second process on a plurality of second memory cells provided in the first storage area, and in response to a request for a random number, a third process on a plurality of third memory cells provided in the second storage area; 
 performing a read operation on the third memory cells; and 
 outputting a result of the read operation as the random number, wherein 
 each of the plurality of memory cells stores a plurality of values according to a threshold voltage, the plurality of values including at least a first value and a second value, the second value being adjacent to the first value in relation to the threshold voltage, 
 the first process is a process of storing the first value in the plurality of first memory cells and setting a highest threshold voltage among the threshold voltages of the plurality of first memory cells as a first threshold voltage, 
 the second process is a process of storing the second value in the plurality of second memory cells and setting a lowest threshold voltage among the threshold voltages of the plurality of second memory cells as a second threshold voltage that is higher than the first threshold voltage, 
 the third process is a process in which a lowest threshold voltage among the threshold voltages of the plurality of third memory cells is made lower than the first threshold voltage, and a highest threshold voltage among the threshold voltages of the plurality of third memory cells is made higher than the second threshold voltage, and 
 the read operation on the third memory cells is performed using a read level that is higher than the first threshold voltage and lower than the second threshold voltage. 
 
     
     
       14. The method according to  claim 13 , further comprising:
 setting as the read level a central voltage of a threshold voltage distribution of the plurality of third memory cells. 
 
     
     
       15. The method according to  claim 13 , further comprising:
 generating key information for encrypting data to be written into the nonvolatile memory by using the result read from the second storage area in the read operation using the read level. 
 
     
     
       16. The method according to  claim 13 , further comprising:
 generating a timing for reading data from the nonvolatile memory by using the result read from the second storage area in the read operation using the read level. 
 
     
     
       17. The method according to  claim 13 , wherein
 a threshold voltage distribution width of the plurality of third memory cells is wider than a threshold voltage distribution width of the plurality of second memory cells. 
 
     
     
       18. The method according to  claim 13 , wherein
 the first process is an erase process performed on the plurality of first memory cells.