Memory system with low-complexity decoding and method of operating such memory system

Abstract

Memory controllers, decoders and methods to selectively perform bit-flipping (BF) decoding and min-sum (MS) decoding on codewords of an irregular low-density parity-check (LDPC) code. Bit-flipping (BF) decoding is executed with respect to variable nodes having relatively high column weights. MS decoding is executed with respect to variable nodes having relatively low column weights. A column-weight threshold is used to group the variable nodes into the higher and lower column weight groups. The two decoding techniques exchange results during the overall decoding process.

What is claimed is: 
     
       1. A memory controller, comprising:
 a storage; and 
 a decoder operably coupled to the storage and configured to perform decoding on received codewords of an irregular code having non-uniform column-weight distribution and representable by at least variable nodes; 
 wherein the decoder is further configured to: 
 execute bit-flipping (BF) decoding with respect to a first set of the variable nodes, each variable node in the first set having a column weight that is greater than or equal to a column-weight threshold, and 
 execute min-sum (MS) decoding with respect to a second set of the variable nodes, each variable node in the second set having a column weight that is less than the column-weight threshold, 
 wherein the first and second sets of variable nodes are mutually exclusive sets respectively grouped into two sets before decoding begins such that the first set of variable nodes all have a high column weight that is greater than or equal to a column-weight threshold and the second set of variable nodes all have a low column weight that is less than the column-weight threshold, and 
 wherein, in each decoding iteration, the decoder selectively executes one of the BF decoding and the MS decoding based on determining whether a set of variable nodes associated with decoding belong to the first set of the variable nodes having the high column weight or the second set of the variable nodes having the low column weight. 
 
     
     
       2. The memory controller of  claim 1 , wherein the irregular code is an irregular low-density parity-check (LDPC) code. 
     
     
       3. The memory controller of  claim 1 , wherein results of the BF decoding and the MS decoding are exchanged during decoding. 
     
     
       4. The memory controller of  claim 1 , wherein the decoder executes BF decoding to update decisions of the variable nodes in the first set. 
     
     
       5. The memory controller of  claim 1 , wherein the decoder executes MS decoding to update decisions of the variable nodes in the second set. 
     
     
       6. A decoder for decoding received codewords of an irregular code having non-uniform column-weight distribution and representable by at least variable nodes, the decoder comprising:
 a bit-flipping (BF) decoding module configured to execute BF decoding with respect to a first set of the variable nodes, each variable node in the first set having a column weight that is greater than or equal to a column-weight threshold; and 
 a min-sum (MS) decoding module configured to execute MS decoding with respect to a second set of the variable nodes, each variable node in the second set having a column weight that is less than the column-weight threshold, 
 wherein the first and second sets of variable nodes are mutually exclusive sets respectively grouped into two sets before decoding begins such that the first set of variable nodes all have a high column weight that is greater than or equal to a column-weight threshold and the second set of variable nodes all have a low column weight that is less than the column-weight threshold, and 
 wherein, in each decoding iteration, the decoder selectively executes one of the BF decoding and the MS decoding based on determining whether a set of variable nodes associated with decoding belong to the first set of the variable nodes having the high column weight or the second set of the variable nodes having the low column weight. 
 
     
     
       7. The decoder of  claim 6 , wherein the BF decoding module is integrated in a BF decoder that is part of the decoder. 
     
     
       8. The decoder of  claim 7 , wherein the MS decoding module is integrated in an MS decoder that is part of the decoder. 
     
     
       9. The decoder of  claim 6 , wherein the BF and MS decoding modules each comprises a sub-algorithm embodied in the decoder. 
     
     
       10. The decoder of  claim 6 , wherein the BF and MS decoding modules exchange results during decoding. 
     
     
       11. A method for decoding received codewords of an irregular code having non-uniform column-weight distribution and representable by variable nodes and check nodes, the method comprising the steps of:
 updating decisions of a first set of the variable nodes, using a bit-flipping (BF) algorithm, to obtain updated decisions of the variable nodes of the first set; 
 updating a syndrome vector for the codewords using the updated decisions of the variable nodes of the first set; 
 updating messages between the check nodes and a second set of variable nodes, using a min-sum (MS) algorithm, to obtain updated decisions of the variable nodes of the second set; and 
 updating the syndrome vector using the update decisions of the variable nodes of the second set, 
 wherein the first and second sets of variable nodes are mutually exclusive sets respectively grouped into two sets before decoding begins such that the first set of variable nodes all have a high column weight that is greater than or equal to a column-weight threshold and the second set of variable nodes all have a low column weight that is less than the column-weight threshold, and 
 wherein, in each decoding iteration, one of the BF algorithm and the MS algorithm is selectively used for decoding the first set of the variable nodes having the high column weight or the second set of the variable nodes having the low column weight. 
 
     
     
       12. The method of  claim 11 , wherein the irregular code is an irregular low-density parity-check (LDPC) code. 
     
     
       13. The method of  claim 11 , wherein the BF algorithm and the MS algorithm exchange decoding results. 
     
     
       14. The method of  claim 11 , further comprising:
 determining whether or not all syndrome bits of the syndrome vector are zero, and when it is determined that not all syndrome bits are zero, performing another iteration of decoding up to a maximum number of iterations. 
 
     
     
       15. The method of  claim 11 , further comprising:
 calculating the syndrome vector before updating decisions of the first set of the variable nodes. 
 
     
     
       16. The method of  claim 11 , wherein the first set of variable nodes having the high column weight are processed with the bit-flipping (BF) algorithm.