Data path dynamic range optimization

Abstract

Systems and methods are disclosed for full utilization of a data path's dynamic range. In certain embodiments, an apparatus may comprise a circuit including a first filter to digitally filter and output a first signal, a second filter to digitally filter and output a second signal, a summing node, and a first adaptation circuit. The summing node combine the first signal and the second signal to generate a combined signal at a summing node output. The first adaptation circuit may be configured to receive the combined signal, and filter the first signal and the second signal to set a dynamic amplitude range of the combined signal at the summing node output by modifying a first coefficient of the first filter and a second coefficient of the second filter based on the combined signal.

What is claimed is: 
     
       1. An apparatus comprising:
 a data channel circuit configured to receive and process a signal to generate a bit sequence encoded in the signal, the data channel circuit including:
 an adaptation circuit configured to adjust an amplitude of the signal as it passes between components of the data channel circuit to constrain the amplitude of the signal when it is output from a first component to approximately match an amplitude range that a second component is configured to receive, the adaptation circuit including:
 a pulse response filter configured to generate a noiseless waveform of the signal based on an expected bit sequence for the signal; 
 a summing node configured to combine an output of the pulse response filter and the signal received at the adaptation circuit to generate an error value based on a difference between the signal received at the adaptation circuit and the noiseless waveform; 
 a pulse response filter adaptation circuit configured to:
 receive the error value; 
 adjust a coefficient of the pulse response filter to adjust the noiseless waveform for the signal; and 
 
 a gain control circuit configured to adjust an amplitude output of the first component based on the error value. 
 
 
 
     
     
       2. The apparatus of  claim 1  further comprising:
 the first component is a signal filter circuit configured to modify the signal based on coefficients of the filter; and 
 the adaptation circuit is configured to adjust the amplitude output of the first component by adjusting at least one coefficient value of the first component. 
 
     
     
       3. The apparatus of  claim 1  further comprising:
 the adaptation circuit further includes:
 a gain adaptation circuit configured to:
 receive the error value; and 
 output a variable gain amplifier (VGA) control signal from the adaptation circuit to the first component to adjust the amplitude output of the first component, via a VGA gain applied by the first component to the signal, based on the error value. 
 
 
 
     
     
       4. The apparatus of  claim 3  further comprising:
 the adaptation circuit further configured to jointly adapt the pulse response filter and the first component to drive the error value towards zero. 
 
     
     
       5. The apparatus of  claim 1  further comprising:
 the data channel circuit further including:
 the first component, wherein the first component is an analog front end (AFE); and 
 the second component, wherein the second component is an analog to digital converter (ADC). 
 
 
     
     
       6. The apparatus of  claim 5  further comprising:
 the data channel circuit is a read/write (R/W) channel of a multi-sensor magnetic recording (MSMR) data storage device configured to receive a plurality of signals corresponding to a plurality of read heads, the plurality of signals including the signal, wherein the data channel circuit includes: 
 a plurality of AFEs and ADCs corresponding to the plurality of signals, the plurality of AFEs and ADCs including the first component and the second component; and 
 a plurality of adaptation circuits configured to adjust amplitudes of the plurality of signals output from each of the plurality of AFEs to approximately matches amplitude ranges accepted by each of the corresponding plurality of ADCs. 
 
     
     
       7. The apparatus of  claim 6  comprising the data channel circuit further including:
 a second summing node configured to combine outputs from a first ADC and a second ADC of the plurality of ADCs and output a combined signal; 
 a second adaptation circuit configured to:
 receive the combined signal from the second summing node; and 
 adjust amplitudes of a first signal sent from a first AFE to the first ADC and a second signal sent from a second AFE to the second ADC to set a dynamic amplitude range of the combined signal at an output of the second summing node by modifying a first coefficient of the first AFE and a second coefficient of the second AFE based on the combined signal. 
 
 
     
     
       8. The apparatus of  claim 5  further comprising the adaptation circuit configured to set the amplitude of the signal when it is output from the AFE to be slightly in excess of the of the amplitude range accepted by the ADC to provide improved resolution for the signal around 0 millivolts (mV). 
     
     
       9. The apparatus of  claim 1  further comprising the signal is received at the adaptation circuit from an output of the second component. 
     
     
       10. The apparatus of  claim 1  further comprising:
 the pulse response filter adaptation circuit is further configured to adapt a selected coefficient of the pulse response filter to fix an absolute sum of coefficients of the pulse response filter to a selected constant value K, in order to set the amplitude of the signal output from the first component to K through joint adaptation of the first component and the pulse response filter. 
 
     
     
       11. A method comprising:
 constraining an amplitude of a signal to one or more selected amplitude ranges at selected points along a data channel circuit via addition of filter adaptation modules (FAMs), including: 
 configuring a FAM to constrain the amplitude of the signal via performing joint adaptation of:
 1) a filter providing the signal to the FAM, and 
 2) a pulse response filter of the FAM configured to generate a noiseless waveform of the signal based on an expected bit sequence for the signal, 
 
 based on an error value generated from a difference between the signal received at the FAM and the noiseless waveform; and 
 adding a first FAM at the outputs of each analog-to-digital converter (ADC), with an output of the first FAM applied to an analog front end (AFE) that provides a first signal to the ADC, to control the amplitude of the signal output from the AFE and the ADC. 
 
     
     
       12. The method of  claim 11  further comprising:
 adding a second FAM at the outputs of each summing junction that sums outputs of at least two filters, with the output of the second FAM applied to the at least two filters, to control the amplitudes of the signals from the at least two filters to the each summing junction. 
 
     
     
       13. The method of  claim 12  further comprising:
 adding a first filter before each input to a first summing junction for which the input:
 does not already have a filter; or 
 includes a filter whose amplitude output is already constrained by a FAM; and 
 
 adding the second FAM at the output of the first summing junction to control the amplitude of the signals from each filter that inputs a signal to the first summing junction. 
 
     
     
       14. The method of  claim 13  further comprising:
 adding a third FAM at the output of each unconstrained filter that provides an output to a signal processing circuit and whose output amplitude is not already constrained by an FAM, with the output of the third FAM applied to the unconstrained filter to control the amplitude of the signals from the unconstrained filter to the signal processing circuit. 
 
     
     
       15. The method of  claim 14  further comprising:
 adding a second filter before each signal processing circuit that:
 receives a signal that is not constrained by an FAM; and 
 has no filter available to constrain via an FAM; and 
 
 adding the third FAM at the output of the second filter to control the amplitude of the signal from the second filter to a respective signal processing circuit. 
 
     
     
       16. An apparatus comprising:
 a data channel circuit configured to process a plurality of signals, the data channel circuit including:
 a first signal filter configured to adjust an amplitude of a first signal output from the first signal filter to a first input of a first summing circuit; 
 a second signal filter configured to adjust an amplitude of a second signal output from the second signal filter to a second input of the first summing circuit; 
 the first summing circuit configured to:
 combine the first signal and the second signal to create a combined signal; 
 output the combined signal; 
 
 a pulse response filter configured to output a noiseless waveform signal to an error signal generation circuit; 
 the error signal generation circuit configured to:
 receive the combined signal and the noiseless waveform signal; 
 output an error value based on a difference between the combined signal and the noiseless waveform; and 
 
 the data channel circuit is configured to adjust coefficients of the first signal filter and the second signal filter independently, based on the error value, in order to constrain the combined signal to a first selected amplitude range. 
 
 
     
     
       17. The apparatus of  claim 16  further comprising the first filter and the second filter are arranged in parallel. 
     
     
       18. The apparatus of  claim 17  comprising the data channel circuit further including:
 a first adaptation circuit configured to:
 receive the error value; 
 adjust the coefficients of the first signal filter based on the error value, without constraining the amplitude range of the first signal; 
 
 a second adaptation circuit configured to:
 receive the error value; 
 adjust the coefficients of the second signal filter based on the error value, without constraining the amplitude range of the second signal; and 
 
 the first adaptation circuit and the second adaptation circuit configured to adjust the respective coefficients in order to constrain the combined signal to the first selected amplitude range. 
 
     
     
       19. The apparatus of  claim 18  comprising the data channel circuit further including:
 a pulse response filter adaptation circuit configured to:
 receive the error value from the error signal generation circuit; and 
 adjust coefficients of the pulse response filter to constrain an amplitude of the noiseless waveform signal to a second selected amplitude range. 
 
 
     
     
       20. The apparatus of  claim 19  comprising the data channel circuit further including:
 a third signal filter, parallel to the first signal filter and the second signal filter, configured to adjust an amplitude of a third signal output from the third signal filter to a first input of a second summing circuit; 
 the first summing circuit configured to output the combined signal to the second summing circuit; 
 the second summing circuit configured to:
 add the third signal to the combined signal to update the combined signal; 
 output the combined signal to the error signal generation circuit; 
 
 a third adaptation circuit configured to:
 receive the error value; 
 adjust the coefficients of the third signal filter based on the error value, without constraining the amplitude range of the third signal; and 
 
 the first adaptation circuit, the second adaptation circuit, and the third adaptation circuit configured to adjust the respective coefficients in order to constrain the combined signal to the first selected amplitude range.