Hardware complexity reduction technique for successive cancellation list decoders

Abstract

A hardware complexity reduction method for successive cancellation list decoders (SCL) is provided. In path pruning stages of an SCL decoding, L paths with smallest path metrics out of 2L candidate paths are chosen as surviving candidate paths as in a conventional SCL algorithm. Moreover, path indexes of L surviving candidate paths are provided in a sorted manner according to indexes at an output of a sorter module. After a path pruning, instead of L-to-1 multiplexers, (L/2+1)-to-1 multiplexers are deployed to perform copying operations of any required elements stored in dedicated registers of the L surviving candidate paths.

The invention claimed is: 
     
       1. A successive cancellation list hardware decoder for polar codes, wherein the decoder comprises:
 a sorter module configured to perform a path pruning by choosing L paths with smallest path metrics out of 2L candidate paths as surviving candidate paths, wherein the sorter module is further configured to perform a sorting operation after the path pruning to sort the L surviving candidate paths according to path indexes of the L surviving candidate paths before the path pruning, wherein the sorted L surviving candidate paths are split from other paths; 
 at least one multiplexer bank, wherein each of the at least one multiplexer bank includes exactly L multiplexers, and each of the multiplexers is a (L/2+1)-to-1 multiplexer that takes predetermined L/2+1 paths out of the sorted L surviving candidate paths as input, and the at least one multiplexer bank is configured to perform copying operations of contents of dedicated storage elements, wherein the contents of the dedicated storage elements are intermediate Log-Likelihood Ratio values, decoded bits, partial-sums, and pointer registers for each path after the path pruning according to the path indexes of the sorted L surviving candidate paths. 
 
     
     
       2. The successive cancellation list decoder according to  claim 1 , wherein the sorter module performs the sorting operation of the path indexes of the L surviving candidate paths in an ascending order. 
     
     
       3. The successive cancellation list decoder according to  claim 1 , wherein the sorter module performs the sorting operation of the path indexes of the L surviving candidate paths in a descending order. 
     
     
       4. The successive cancellation list decoder according to  claim 1 , wherein the at least one multiplexer bank has the number of L (L/2+1)-to- 1  multiplexers configured to copy intermediate Log-Likelihood Ratio values from the 2L candidate paths. 
     
     
       5. The successive cancellation list decoder according to  claim 1 , wherein the at least one multiplexer bank has the number of L (L/2+1)-to-1 multiplexers configured to copy the pointer registers from the 2L candidate paths. 
     
     
       6. The successive cancellation list decoder according to  claim 1 , wherein the at least one multiplexer bank has the number of L (L/2+1)-to-1 multiplexers configured to copy partial sum bits from the 2L candidate paths. 
     
     
       7. The successive cancellation list decoder according to  claim 1 , wherein the at least one multiplexer bank has the number of L (L/2+1)-to-1 multiplexers configured to copy the decoded bits from the 2L candidate paths.