Semiconductor storage apparatus, product-sum calculation apparatus, and electronic equipment

Abstract

To provide a semiconductor storage apparatus, a product-sum calculation apparatus, and electronic equipment in which memory cells are highly integrated and highly densified. A semiconductor storage apparatus including: a first transistor including a first gate electrode via a ferroelectric film on an activation region including source or drain regions; and a second transistor including source or drain regions in an activation layer provided on the first gate electrode and a second gate electrode on the activation layer via an insulating film.

The invention claimed is: 
     
       1. A semiconductor storage apparatus, comprising:
 a first transistor including:
 a ferroelectric film on an activation region, wherein the activation region extends in a first direction on a semiconductor substrate; 
 a first source region or a first drain region in the activation region; and 
 a first gate electrode on the ferroelectric film, wherein the first gate electrode extends in a second direction orthogonal to the first direction; and 
 
 a second transistor including:
 an activation layer on the first gate electrode; 
 a second source region or a second drain region in the activation layer; 
 an insulating film on the activation layer; and 
 a second gate electrode on the activation layer via the insulating film. 
 
 
     
     
       2. The semiconductor storage apparatus according to  claim 1 , wherein the activation layer includes a semiconductor material. 
     
     
       3. The semiconductor storage apparatus according to  claim 1 , wherein the second gate electrode extends in the first direction. 
     
     
       4. The semiconductor storage apparatus according to  claim 1 , wherein
 one of the first source region or the first drain region of the first transistor is electrically connected to a source line that extends in the second direction, and 
 another of the first source region or the first drain region of the first transistor is electrically connected to a second bit line that extends in the first direction. 
 
     
     
       5. The semiconductor storage apparatus according to  claim 1 , wherein
 one of the second source region or the second drain region of the second transistor is electrically connected to the first gate electrode, and 
 another of the second source region or the second drain region of the second transistor is electrically connected to a first bit line that extends in the second direction. 
 
     
     
       6. The semiconductor storage apparatus according to  claim 1 , wherein
 the first source region or the first drain region of the first transistor are in the activation region on both sides of the first gate electrode, and 
 the second source region or the second drain region of the second transistor are in the activation layer on both sides of the second gate electrode. 
 
     
     
       7. The semiconductor storage apparatus according to  claim 1 , wherein the activation layer is on the first gate electrode and the semiconductor substrate along an outer shape of the first gate electrode and the semiconductor substrate. 
     
     
       8. The semiconductor storage apparatus according to  claim 1 , wherein the second gate electrode is on the activation layer and the semiconductor substrate along an outer shape of the activation layer and the semiconductor substrate via the insulating film. 
     
     
       9. The semiconductor storage apparatus according to  claim 1 , wherein
 each of the first source region or the first drain region of the first transistor is a same conductivity type region, and 
 each of the second source region or the second drain region of the second transistor is a same conductivity type region. 
 
     
     
       10. The semiconductor storage apparatus according to  claim 1 , wherein the second transistor is a thin film transistor. 
     
     
       11. The semiconductor storage apparatus according to  claim 1 , wherein a plurality of sets of the first transistor and the second transistor is repeatedly stacked. 
     
     
       12. A product-sum calculation apparatus, comprising:
 a first transistor including:
 a ferroelectric film on an activation region, wherein the activation region extends in a first direction on a semiconductor substrate; 
 a first source region or a first drain region in the activation region; and 
 a first gate electrode on the ferroelectric film, wherein the first gate electrode extends in a second direction orthogonal to the first direction; and 
 
 a second transistor including:
 an activation layer on the first gate electrode; 
 a second source region or a second drain region in the activation layer; 
 an insulating film on the activation layer; and 
 a second gate electrode on the activation layer via the insulating film. 
 
 
     
     
       13. An electronic equipment, comprising:
 a semiconductor storage apparatus including:
 a first transistor including:
 a ferroelectric film on an activation region, wherein the activation region extends in a first direction on a semiconductor substrate; 
 a first source region or a first drain region in the activation region; and 
 a first gate electrode on the ferroelectric film, wherein the first gate electrode extends in a second direction orthogonal to the first direction; and 
 
 a second transistor including:
 an activation layer on the first gate electrode; 
 a second source region or a second drain region in the activation layer; 
 an insulating film on the activation layer; and 
 a second gate electrode on the activation layer via the insulating film. 
 
 
 
     
     
       14. A semiconductor storage apparatus, comprising:
 a first transistor including:
 a ferroelectric film on an activation region, wherein the activation region extends in a first direction on a semiconductor substrate; 
 a first source region or a first drain region in the activation region; and 
 a first gate electrode on the ferroelectric film, wherein the first gate electrode extends in a second direction orthogonal to the first direction; and 
 
 a second transistor including:
 an activation layer on the first gate electrode; 
 a second source region or a second drain region in the activation layer; 
 an insulating film on the activation layer; and 
 a second gate electrode on the activation layer via the insulating film, wherein the second gate electrode extends in the first direction.