TFT array substrate, fabricating method thereof, and display panel thereof

Abstract

The present invention provides a thin film transistor (TFT) array substrate including a base layer. A function layer is disposed on the base layer, and a planarization layer is disposed on the function layer. The planarization layer includes a vertical insertion extending into the function layer, and a side of the vertical insertion horizontally extends outwardly into the function layer to from a horizontal insertion. The invention provides a TFT array substrate, which adopts a novel inter-layers structure arrangement, which effectively reduces risk of potential mutual detachment between different layers, thereby improving product stability.

What is claimed is: 
     
       1. A thin film transistor (TFT) array substrate comprising:
 a base layer having a function layer disposed on the base layer, and a planarization layer disposed on the function layer, 
 wherein the planarization layer comprises a vertical insertion extending into the function layer, a side of the vertical insertion horizontally extends outwardly into the function layer to form a horizontal insertion, and the horizontal insertion horizontally protrudes from a sidewall of the vertical insertion above the horizontal insertion; 
 wherein the function layer comprises a metal layer and an insulating layer which are laminated, and the horizontal insertion is disposed in the insulating layer; and 
 wherein the insulating layer comprises a first insulating layer and a second insulating layer disposed on the first insulating layer, and the horizontal insertion comprises a first horizontal insertion and a second horizontal insertion, wherein the first horizontal insertion is disposed in the first insulating layer, and the second horizontal insertion is disposed in the second insulating layer. 
 
     
     
       2. The TFT array substrate according to  claim 1 , wherein both sides of the vertical insertion extend outwardly to respectively form a first horizontal insertion and a second horizontal insertion which pertain to the horizontal insertion and are oppositely disposed. 
     
     
       3. The TFT array substrate according to  claim 1 , wherein the insulating layer comprises a first insulating layer and a second insulating layer disposed on the first insulating layer, and the horizontal insertion is disposed in the first insulating layer. 
     
     
       4. The TFT array substrate according to  claim 1 , wherein the insulating layer comprises a first insulating layer and a second insulating layer disposed on the first insulating layer, and the horizontal insertion is disposed in the second insulating layer. 
     
     
       5. The TFT array substrate according to  claim 1 , wherein the function layer further comprises an interlayer dielectric layer, the planarization layer is disposed on the interlayer dielectric layer, and the horizontal insertion is disposed in the interlayer dielectric layer. 
     
     
       6. The TFT array substrate according to  claim 1 , wherein the function layer comprises a metal layer, an insulating layer, and an interlayer dielectric layer which are laminated, wherein the planarization layer is disposed on the interlayer dielectric layer, and the horizontal insertion is disposed in the insulating layer or the interlayer dielectric layer. 
     
     
       7. A display panel comprising the TFT array substrate according to  claim 1 . 
     
     
       8. A method of fabricating the thin film transistor (TFT) array substrate according to  claim 1 , comprising the steps of:
 step S 1 , providing the base layer and forming the function layer on the base layer, wherein when forming a metal layer in the function layer, an electrode layer and a reserved metal layer at a predetermined position are retained in the function layer; 
 step S 2 , performing a front exposure development on the function layer, and forming a via hole extending into the function layer, wherein a side of the via hole is in contact with the reserved metal layer; and 
 step S 3 , removing the reserved metal layer, and performing coating of the planarization layer, the planarization layer filling the via hole and the predetermined position for the reserved metal layer, wherein after the filling is completed, a portion of the planarization layer filled in the via hole is the vertical insertion and a portion of the planarization layer filled in the predetermined position for the reserved metal layer is the horizontal insertion that is in contact with the side of the vertical insertion.