Controller and memory system

Abstract

A controller includes an Error Correction Code (ECC) encoder adding a first parity to data to generate a data set, and encoding the data set to generate a first parity data set, a buffer temporarily storing the first parity data set, an ECC decoder decoding the first parity data set received from the buffer to generate a decoded data set, a first checker performing a Low Density Parity Check (LDPC) encoding on the decoded data set to generate an LDPC data set to which a second parity is added, and a second checker performing a syndrome check operation on the LDCP data set including the first and second parities.

What is claimed is: 
     
       1. A controller comprising:
 a host controller encrypting a first data which is output from a host, adding a parity to encrypted data, and encoding the encrypted data; 
 a first buffer temporarily storing the encrypted data which is output from the host controller; and 
 a memory controller adding an additional parity to the encrypted data, which is output from the first buffer, to perform an error check operation, 
 wherein the memory controller outputs the error-checked data as a second data when no error is found. 
 
     
     
       2. The controller of  claim 1 , wherein the host controller comprises:
 an external Cyclic Redundancy Check (CRC) encoder adding a first parity to the first data to generate a first parity data set; 
 an encryption encoder encrypting the first parity data set to output the encrypted data set; and 
 a first external cyclic redundancy check (ECC) encoder adding a second parity to the encrypted data set, encoding the parity-added encrypted data set to generate a second parity data set, and outputting the second parity data set as the encrypted data to the first buffer. 
 
     
     
       3. The controller of  claim 1 , wherein the first buffer includes a volatile memory or a non-volatile memory. 
     
     
       4. The controller of  claim 3 , wherein the memory controller comprises:
 a first ECC decoder decoding the second parity data set which is received from the first buffer; 
 a first checker performing a low density parity check (LDPC) encoding on the decoded data set to generate an LDPC data set to which an LDPC parity is added; and 
 a second checker performing a syndrome check operation on the LDPC data set including the first, second, and LDPC parities. 
 
     
     
       5. The controller of  claim 4 , wherein the second checker:
 when the syndrome check operation passes, outputs the LDPC data set as the second data: and 
 when the syndrome check operation fails, changes a check node value until the syndrome check operation passes. 
 
     
     
       6. The controller of  claim 5 , wherein the memory controller further comprises:
 a third checker performing an error correction operation on a third data which is read from a memory device, and generating the decoded data set from which the LDPC parity is removed; and 
 a second ECC encoder encoding the decoded data set which is output from the third checker. 
 
     
     
       7. The controller of  claim 6 , further comprising a second buffer temporarily storing the encoded data set which is output from the second ECC encoder. 
     
     
       8. The controller of  claim 7 , wherein the second buffer includes a volatile memory or a non-volatile memory. 
     
     
       9. The controller of  claim 7 , wherein the host controller further comprises:
 a second ECC decoder decoding the encoded data set which is received from the second buffer to generate a data set from which the second parity is removed; 
 an encryption decoder decrypting the data set which is output from the second ECC decoder; and 
 an external CRC decoder removing the first parity from the data set which is output from the encryption decoder to output the parity-removed data set to the host.