Method and apparatus for synchronous signaling between link partners in a high-speed interconnect

Abstract

Loop timing is performed in a Reconciliation Sublayer (RS) so that the transmit clock frequency can be adjusted to be equal to the receive clock frequency for the entire PHY (including the physical coding sublayer (PCS)). One of two partners is selected to be the timing Slave to the other. If only one partner is capable of loop timing, that partner becomes the Slave. If both partners are capable of loop timing, symmetry breaking can be used to determine which partner should become Slave.

What is claimed is: 
     
       1. An apparatus comprising:
 port circuitry in a slave link partner, to communicate with a master link partner, the port circuitry including:
 a transmit clock having a transmit clock frequency; and 
 a loop timing controller in a physical coding sublayer (PCS) module, the loop timing controller configured to receive a recovered receive clock from the master link partner and to initialize loop timing with the master link partner to adjust the transmit clock frequency so that a receive clock frequency of the recovered receive clock from the master link partner is equal to the transmit clock frequency. 
 
 
     
     
       2. The apparatus of  claim 1 , wherein the master link partner is selected to be a timing slave. 
     
     
       3. The apparatus of  claim 1 , wherein the loop timing is initialized through use of a loop timing ordered set. 
     
     
       4. The apparatus of  claim 1 , wherein if both the slave link partner and the master link partner are capable of loop timing, symmetry breaking to be performed to determine if the slave link partner or the master link partner is designated a Slave. 
     
     
       5. The apparatus of  claim 1 , wherein the loop timing is deactivated in the slave link partner upon detection that the master link partner is configured to perform the loop timing. 
     
     
       6. The apparatus of  claim 1 , wherein the transmit clock frequency is adjusted prior to transfer of data between the slave link partner and the master link partner. 
     
     
       7. The apparatus of  claim 1 , wherein if the slave link partner is capable of loop timing, the slave link partner is designated a slave. 
     
     
       8. A system comprising:
 a memory module, the memory module comprising at least one volatile memory integrated circuit, the volatile memory integrated circuit to store a message; and 
 port circuitry in a slave link partner, to send the message stored in the volatile memory integrated circuit to a master link partner, the port circuitry including:
 a transmit clock having a transmit clock frequency; and 
 a loop timing controller in a physical coding sublayer (PCS) module, the loop timing controller configured to receive a recovered receive clock from the master link partner and to initialize loop timing with the master link partner to adjust the transmit clock frequency so that a receive clock frequency of the recovered receive clock from the master link partner is equal to the transmit clock frequency. 
 
 
     
     
       9. An apparatus comprising:
 a transmit clock having a transmit clock frequency; and 
 a loop timing controller in a physical coding sublayer (PCS) module, the loop timing controller configured to adjust the transmit clock frequency to be equal to a receive clock frequency of a recovered receive clock for a PHY. 
 
     
     
       10. A system comprising:
 a slave link partner; 
 port circuitry in the slave link partner, to communicate via a copper cable with a master link partner, the port circuitry including:
 a transmit clock having a transmit clock frequency; and 
 a loop timing controller in a physical coding sublayer (PCS) module, the loop timing controller configured to receive a recovered receive clock from the master link partner and to initialize loop timing with the master link partner to adjust the transmit clock frequency so that a receive clock frequency of the recovered receive clock from the master link partner is equal to the transmit clock frequency. 
 
 
     
     
       11. The system of  claim 10 , wherein the master link partner is selected to be a timing Slave. 
     
     
       12. The system of  claim 10 , wherein the loop timing is initialized through use of a loop timing ordered set. 
     
     
       13. The system of  claim 10 , wherein if both the slave link partner and the master link partner are capable of loop timing, symmetry breaking to be performed to determine if the slave link partner or the master link partner is designated a Slave. 
     
     
       14. The system of  claim 10 , wherein the loop timing is deactivated in the slave link partner upon detection that the master link partner is configured to perform the loop timing. 
     
     
       15. The system of  claim 10 , wherein if the slave link partner is capable of the loop timing, the slave link partner is designated a slave. 
     
     
       16. A method comprising:
 communicating by port circuitry in a slave link partner with a master link partner; 
 receiving a recovered receive clock from the master link partner; and 
 initializing loop timing, by a loop timing controller in a physical coding sublayer (PCS) module, with the master link partner to adjust a transmit clock frequency so that a receive clock frequency of the recovered receive clock from the master link partner is equal to the transmit clock frequency. 
 
     
     
       17. The method of  claim 16 , wherein if both the slave link partner and the master link partner are capable of the loop timing, symmetry breaking to be performed to determine if the slave link partner or the master link partner is designated a Slave. 
     
     
       18. The method of  claim 16 , wherein the master link partner is selected to be a timing slave. 
     
     
       19. The method of  claim 16 , wherein the loop timing is initialized through use of a loop timing ordered set. 
     
     
       20. The method of  claim 16 , wherein if the slave link partner is capable of the loop timing, the slave link partner is designated a slave. 
     
     
       21. The method of  claim 16 , wherein the loop timing is deactivated in the slave link partner upon detection that the master link partner is configured to perform the loop timing. 
     
     
       22. A computer-readable non-transitory medium for storing machine-executable instructions that, cause a system to:
 send, from a slave link partner, a Link-Layer Discovery Protocol (LLDP) frame to a master link partner, the frame to include a loop timing message that includes a control, length, and value (TLV) information string with message type bits set to indicate the slave link partner is a timing slave; and 
 in response to an acknowledge message received from the master link partner, activate loop timing in a physical coding sublayer (PCS) module with the slave link partner as the timing slave. 
 
     
     
       23. The computer-readable non-transitory medium of  claim 22 , further comprising:
 if a response is not received from the master link partner within a selected time, activate loop timing with the slave link partner as the timing slave. 
 
     
     
       24. The computer-readable non-transitory medium of  claim 22 , further comprising:
 in response to a denial message received from the master link partner, loop timing is not enabled with the slave link partner.