Memory device including test control circuit

Abstract

A memory device includes a memory cell array, an input/output circuit, a test register circuit, and a test control block. The memory cell array is suitable for storing data. The input/output circuit is suitable for inputting and outputting the data stored in the memory cell array. The test register circuit is suitable for testing the input/output circuit. The test control block includes a replica circuit having a replica configuration of the test register circuit by modeling the test register circuit, and is suitable for generating the data to test the test register circuit.

What is claimed is: 
     
       1. A memory device comprising:
 a memory cell array suitable for storing data; 
 an input/output circuit suitable for inputting and outputting the data stored in the memory cell array; 
 a test register circuit suitable for testing the input/output circuit; and 
 a test control block comprising a replica circuit having a replica configuration of the test register circuit by modeling the test register circuit, and suitable for generating the data to test the test register circuit, 
 wherein the test control block is suitable for testing the test register circuit by generating pattern data, transmitting the generated pattern data to the test register circuit and the replica circuit, and comparing the data which are fed back from the test register circuit to the data which are fed back from the replica circuit. 
 
     
     
       2. The memory device of  claim 1 , wherein the test control block is suitable for testing the memory cell array by generating pattern data and random data, transmitting the generated pattern data and random data to the memory cell array, and comparing the data fed back from the memory cell array to the generated pattern data and random data. 
     
     
       3. The memory device of  claim 1 , wherein the test control block comprises a BIST (Built-In Self Test) circuit. 
     
     
       4. The memory device of  claim 1 , wherein the test register circuit and the replica circuit comprise an LFSR (Linear Feedback Shift Register) and an MISR (Multiple Input Signature Register). 
     
     
       5. A memory device comprising:
 a memory cell array suitable for storing data; 
 an input/output circuit suitable for inputting and outputting the data stored in the memory cell array; 
 a test register circuit suitable for testing the input/output circuit; 
 a data generation circuit suitable for generating pattern data and random data during a test operation; 
 a selection circuit suitable for selectively outputting the pattern data and the random data to the test register circuit and the memory cell array during the test operation; and 
 a replica circuit having a replica configuration of the test register circuit by modeling the test register circuit, and suitable for generating operation data based on output data of the data generation circuit, 
 wherein the replica circuit is capable of testing the test register circuit based on a comparison of data outputted from the test register circuit with data outputted from the replica circuit. 
 
     
     
       6. The memory device of  claim 5 , further comprising:
 a pattern decoding circuit suitable for generating a select signal, an enable signal, and a code value according to the test operation, 
 wherein the pattern decoding circuit is suitable for activating the select signal during the test operation of the test register circuit, and for deactivating the select signal during the test operation of the memory cell array. 
 
     
     
       7. The memory device of  claim 6 , wherein the data generation circuit comprises:
 a pattern generation unit suitable for generating the pattern data based on the code value when the enable signal is activated; and 
 an LFSR (Linear Feedback Shift Register) suitable for generating the random data based on the code value, when the enable signal is deactivated. 
 
     
     
       8. The memory device of  claim 7 , wherein the pattern generation unit comprises:
 a plurality of registers; 
 a plurality of operation units suitable for performing a corresponding operation on values stored in the plurality of registers and feedback data of the pattern data; and 
 a multiplexer suitable for selecting one of the plurality of operation units based on the code value and outputting an output of the selected operation unit as the pattern data, in response to the enable signal. 
 
     
     
       9. The memory device of  claim 6 , wherein the selection circuit comprises:
 a first transmitter/receiver suitable for transmitting the output data of the data generation circuit to the test register circuit, and for receiving data of the test register circuit as feedback data, when the select signal is activated; and 
 a second transmitter/receiver suitable for transmitting the output data of the data generation circuit to the memory cell array, and for receiving data of the memory cell array as the feedback data, when the select signal is deactivated. 
 
     
     
       10. The memory device of  claim 9 , further comprising:
 a comparison circuit suitable for selecting one of the operation data and the output data of the data generation circuit in response to the select signal, comparing the selected data to the feedback data, and outputting a detection result. 
 
     
     
       11. A stacked memory device comprising:
 a base die; and 
 a core die stacked on the base die, 
 wherein the base die comprises:
 an interface circuit suitable for transmitting and receiving signals to and from a controller; 
 a test register circuit suitable for testing the interface circuit; and 
 a test control block comprising a replica circuit having a replica configuration of the rest register circuit by modeling the test register circuit, and suitable for generating pattern data and random data to selectively test the test register circuit and the core die during a test operation. 
 
 
     
     
       12. The stacked memory device of  claim 11 , wherein the test control block is suitable for testing the test register circuit by transmitting the pattern data to the test register circuit and the replica circuit and comparing the data which are fed back from the test register circuit to the data which are fed back from the replica circuit. 
     
     
       13. The stacked memory device of  claim 11 , wherein the test control block is suitable for testing the core die by transmitting the pattern data and the random data to the core die and comparing the data which are fed back from the core die to the pattern data and the random data. 
     
     
       14. The stacked memory device of  claim 11 , wherein the test control block comprises:
 a pattern decoding circuit suitable for generating a select signal, an enable signal, and a code value according to the test operation; 
 a data generation circuit suitable for generating the pattern data and the random data based on the code value, in response to the enable signal; and 
 a selection circuit suitable for selectively outputting the pattern data and the random data to the test register circuit and the core die in response to the select signal. 
 
     
     
       15. The stacked memory device of  claim 14 , wherein the pattern decoding circuit is suitable for activating the select signal during a test operation of the test register circuit, and for deactivating the select signal during a test operation of the core die. 
     
     
       16. The stacked memory device of  claim 15 , wherein the data generation circuit comprises:
 a pattern generation unit suitable for generating the pattern data based on the code value when the enable signal is activated; and 
 an LFSR (Linear Feedback Shift Register) suitable for generating the random data based on the code value, when the enable signal is deactivated. 
 
     
     
       17. The stacked memory device of  claim 15 , wherein the selection circuit comprises:
 a first transmitter/receiver suitable for transmitting output data of the data generation circuit to the test register circuit, and for receiving data of the test register circuit as feedback data, when the select signal is activated; and 
 a second transmitter/receiver suitable for transmitting the output data of the data generation circuit to the core die, and for receiving data of the core die as the feedback data, when the select signal is deactivated. 
 
     
     
       18. The stacked memory device of  claim 17 , wherein the test control block further comprises a comparison circuit suitable for selecting one of the output data of the data generation circuit and output data of the replica circuit in response to the select signal, comparing the selected data to the feedback data, and outputting a detection result.