Semiconductor device and manufacturing method of semiconductor device

Abstract

A semiconductor device includes a cell array including a source structure, a peripheral circuit, an interconnection structure located between the cell array and the peripheral circuit and electrically coupled to the peripheral circuit, and a decoupling structure configured to prevent a coupling capacitor that occurs between the cell array and the interconnection structure.

What is claimed is: 
     
       1. A semiconductor device, comprising:
 a cell array including a source structure; 
 a peripheral circuit; 
 an interconnection structure located between the cell array and the peripheral circuit and electrically coupled to the peripheral circuit; and 
 a decoupling structure located between the cell array and the interconnection structure and having an electrically floating state. 
 
     
     
       2. The semiconductor device of  claim 1 , wherein the decoupling structure has a mesh shape. 
     
     
       3. The semiconductor device of  claim 1 , wherein the decoupling structure comprises:
 first conductive patterns; and 
 second conductive patterns crossing the first conductive patterns. 
 
     
     
       4. The semiconductor device of  claim 1 , further comprising an interlayer insulating layer that is interposed between the cell array and the interconnection structure,
 wherein the decoupling structure is formed in the interlayer insulating layer. 
 
     
     
       5. The semiconductor device of  claim 1 , wherein the decoupling structure is electrically separated from the cell array and the interconnection structure. 
     
     
       6. The semiconductor device of  claim 1 , wherein the interconnection structure includes wires that are coupled to a reference voltage generation circuit. 
     
     
       7. The semiconductor device of  claim 6 , wherein the decoupling structure prevents a coupling capacitor between the source structure and the wires. 
     
     
       8. The semiconductor device of  claim 1 , wherein the cell array further includes a bit line and a memory string, and
 wherein the decoupling structure prevents a coupling capacitor between the source structure and the interconnection structure. 
 
     
     
       9. A semiconductor device, comprising:
 a source structure including a first surface and a second surface, the second surface being on an opposite side of the first surface; 
 a cell stacked structure that is located on the first surface of the source structure; 
 a first interconnection structure that is located on the second surface of the source structure; and 
 a decoupling structure located between the source structure and the first interconnection structure and having a mesh shape. 
 
     
     
       10. The semiconductor device of  claim 9 , wherein the decoupling structure has an electrically floating state. 
     
     
       11. The semiconductor device of  claim 9 , wherein the first interconnection structure includes wires that are coupled to a reference voltage generation circuit. 
     
     
       12. The semiconductor device of  claim 11 , wherein the decoupling structure prevents a coupling capacitor between the source structure and the wires. 
     
     
       13. The semiconductor device of  claim 9 , further comprising a ground line applying a ground voltage to the decoupling structure. 
     
     
       14. The semiconductor device of  claim 9 , wherein the decoupling structure comprises:
 first conductive patterns; and 
 second conductive patterns crossing the first conductive patterns. 
 
     
     
       15. The semiconductor device of  claim 9 , wherein the decoupling structure includes openings arranged in a first direction and a second direction, the second direction crossing the first direction. 
     
     
       16. The semiconductor device of  claim 15 , further comprising a second interconnection structure that is located on the first surface of the source structure,
 wherein the second interconnection structure includes a contact plug that is electrically coupled to the first interconnection structure through at least one of the openings. 
 
     
     
       17. The semiconductor device of  claim 9 , further comprising a barrier layer contacting the decoupling structure. 
     
     
       18. The semiconductor device of  claim 9 , wherein the decoupling structure includes a first surface facing the first interconnection structure and a second surface facing the source structure, and
 the decoupling structure further comprises a first barrier layer contacting the first surface and a second barrier layer contacting the second surface.