Chip having a receiver including a hysteresis circuit

Abstract

A hysteresis circuit to be produced within a receiver of a chip is shown. The hysteresis circuit is powered by an overdrive voltage (2VDD), and has a protection circuit, an inverter, and a latch. The input of the hysteresis circuit is coupled to the inverter through the protection circuit, to be transformed into an output, and the latch is coupled to the inverter for positive feedback control. The protection circuit has a first sub-circuit (coupling the input to the inverter to control the pull-up path of the inverter) biased by a first bias voltage that is lower than VDD, and a second sub-circuit (coupling the input to the inverter to control the pull-down path of the inverter) biased by a second bias voltage that is greater than VDD.

What is claimed is: 
     
       1. A chip, comprising:
 a core circuit; and 
 a receiver, coupled to the core circuit, 
 wherein: 
 the receiver includes a hysteresis circuit that processes a signal received from a device external to the chip, the hysteresis circuit is powered by an overdrive voltage which is twice a power supply voltage, and the hysteresis circuit has a protection circuit, an inverter, and a latch; 
 an input of the hysteresis circuit is coupled to the inverter through the protection circuit, to be transformed into an output, and the latch is coupled to the inverter for positive feedback control; 
 the protection circuit has a first sub-circuit biased by a first bias voltage that is lower than the power supply voltage, and a second sub-circuit biased by a second bias voltage that is greater than the power supply voltage; 
 through the first sub-circuit of the protection circuit, the input is coupled to the inverter to control a pull-up path of the inverter; 
 through the second sub-circuit of the protection circuit, the input is coupled to the inverter to control a pull-down path of the inverter; 
 the pull-up path of the inverter is biased by a third bias voltage that is less than the power supply voltage; 
 the pull-down path of the inverter is biased by a fourth bias voltage that is greater than the power supply voltage; 
 the latch has a first sub-circuit biased by a fifth bias voltage that is less than the power supply voltage, and a second sub-circuit biased by a sixth bias voltage that is greater than the power supply voltage; 
 the first sub-circuit of the latch is coupled to the pull-up path of the inverter; and 
 the second sub-circuit of the latch is coupled to the pull-down path of the inverter. 
 
     
     
       2. The chip as claimed in  claim 1 , wherein:
 the third bias voltage is greater than or equal to the first bias voltage; and 
 the fourth bias voltage is less than or equal to the second bias voltage. 
 
     
     
       3. The chip as claimed in  claim 2 , wherein:
 the fifth bias voltage is greater than or equal to the first bias voltage; and 
 the sixth bias voltage is less than or equal to the second bias voltage. 
 
     
     
       4. The chip as claimed in  claim 3 , wherein the inverter comprises:
 a first transistor, having a source terminal coupled to the overdrive voltage, and a gate terminal coupled to an output terminal of the first sub-circuit of the protection circuit; 
 a second transistor, having a source terminal coupled to a power ground voltage, and a gate terminal coupled to an output terminal of the second sub-circuit of the protection circuit; 
 a third transistor, coupling the first transistor to an output terminal of the hysteresis circuit, and having a gate terminal coupled to the third bias voltage; and 
 a fourth transistor, coupling the second transistor to the output terminal of the hysteresis circuit, and having a gate terminal coupled to the fourth bias voltage. 
 
     
     
       5. The chip as claimed in  claim 4 , wherein the first sub-circuit of the latch circuit comprises:
 a fifth transistor, having a source terminal coupled to the drain terminal of the first transistor, and a gate terminal coupled to the output terminal of the hysteresis circuit; and 
 a sixth transistor, coupling a drain terminal of the fifth transistor to the power ground voltage, and having a gate terminal coupled to the fifth bias voltage. 
 
     
     
       6. The chip as claimed in  claim 5 , wherein the first sub-circuit of the latch circuit further comprises:
 a seventh transistor, coupling a drain terminal of the sixth transistor to the power ground voltage, and having a gate terminal controlled by a first control signal, 
 wherein the first sub-circuit of the latch circuit is enabled according to the first control signal. 
 
     
     
       7. The chip as claimed in  claim 6 , wherein:
 the first, third, fifth, and sixth transistors are p-channel metal-oxide-silicon transistors; and 
 the seventh transistor is an n-channel metal-oxide-silicon transistor. 
 
     
     
       8. The chip as claimed in  claim 4 , wherein the second sub-circuit of the latch circuit comprises:
 an eighth transistor, having a source terminal coupled to the drain terminal of the second transistor, and a gate terminal coupled to the output terminal of the hysteresis circuit; and 
 a ninth transistor, coupling a drain terminal of the eighth transistor to the overdrive voltage, and having a gate terminal coupled to the sixth bias voltage. 
 
     
     
       9. The chip as claimed in  claim 8 , wherein the second sub-circuit of the latch circuit further comprises:
 a tenth transistor, coupling a drain terminal of the ninth transistor to the overdrive voltage, and having a gate terminal controlled by a second control signal, 
 wherein the second sub-circuit of the latch circuit is enabled according to the second control signal. 
 
     
     
       10. The chip as claimed in  claim 9 , wherein:
 the second, fourth, eighth, and ninth transistors are n-channel metal-oxide-silicon transistors; and 
 the tenth transistor is a p-channel metal-oxide-silicon transistor. 
 
     
     
       11. The chip as claimed in  claim 4 , wherein the first sub-circuit of the protection circuit comprises:
 an eleventh transistor, coupled between an input terminal of the hysteresis circuit and the gate terminal of the first transistor; and 
 a twelfth transistor, coupling the gate terminal of the first transistor to the first bias voltage, and having a gate terminal coupled to the input terminal of the hysteresis circuit. 
 
     
     
       12. The chip as claimed in  claim 11 , wherein:
 the first, third, eleventh, and twelfth transistors are p-channel metal-oxide-silicon transistors. 
 
     
     
       13. The chip as claimed in  claim 4 , wherein the second sub-circuit of the protection circuit comprises:
 a thirteenth transistor, coupled between an input terminal of the hysteresis circuit and the gate terminal of the second transistor; and 
 a fourteenth transistor, coupling the gate terminal of the second transistor to the second bias voltage, and having a gate terminal coupled to the input terminal of the hysteresis circuit. 
 
     
     
       14. The chip as claimed in  claim 13 , wherein:
 the second, fourth, thirteenth, and fourteenth transistors are n-channel metal-oxide-silicon transistors. 
 
     
     
       15. The chip as claimed in  claim 4 , wherein the inverter further comprises:
 a fifteenth transistor, coupling the first transistor to the third transistor; 
 a sixteenth transistor, coupling the gate terminal of the third transistor to the third bias voltage, and having a gate terminal coupled to the output terminal of the hysteresis circuit; 
 a seventeenth transistor, coupled between the output terminal of the hysteresis circuit and the gate terminal of the third transistor, and having a gate terminal coupled to a gate terminal of the fifteenth transistor; 
 an eighteenth transistor, coupling the second transistor to the fourth transistor; 
 a nineteenth transistor, coupling the gate terminal of the fourth transistor to the fourth bias voltage, and having a gate terminal coupled to the output terminal of the hysteresis circuit; and 
 a twentieth transistor, coupled between the output terminal of the hysteresis circuit and the gate terminal of the fourth transistor, and having a gate terminal coupled to a gate terminal of the eighteenth transistor. 
 
     
     
       16. The chip as claimed in  claim 15 , wherein:
 the first, third, fifteenth, sixteenth, and seventeenth transistors are p-channel metal-oxide-silicon transistors; and 
 the second, fourth, eighteenth, nineteenth, and twentieth transistors are n-channel metal-oxide-silicon transistors.