Semiconductor apparatus and manufacturing method

Abstract

A semiconductor apparatus comprises a first semiconductor region including a first surface and a second surface, in which a semiconductor of a first conductivity type is arranged, a second semiconductor region of the first conductivity type, which is arranged between the first surface and the second surface, a third semiconductor region of a second conductivity type, which is arranged in a region between the second semiconductor region and the second surface and on a side portion of the second semiconductor region, a fourth semiconductor region of the first conductivity type, which is arranged between the first surface and the second surface; and a fifth semiconductor region of the second conductivity type, which is arranged in a region between the fourth semiconductor region and the second surface and on a side portion of the fourth semiconductor region.

What is claimed is: 
     
       1. A semiconductor apparatus comprising:
 a first semiconductor region including a first surface and a second surface, in which a semiconductor of a first conductivity type is arranged; 
 a second semiconductor region of the first conductivity type, which is arranged between the first surface and the second surface; 
 a third semiconductor region of a second conductivity type, which is arranged in a region between the second semiconductor region and the second surface and on a side portion of the second semiconductor region; 
 a fourth semiconductor region of the first conductivity type, which is arranged between the first surface and the second surface; and 
 a fifth semiconductor region of the second conductivity type, which is arranged in a region between the fourth semiconductor region and the second surface and on a side portion of the fourth semiconductor region, 
 wherein the third semiconductor region and the fifth semiconductor region are separated, and 
 a net impurity concentration of the first conductivity type in each of the second semiconductor region and the fourth semiconductor region is lower than a net impurity concentration of the second conductivity type in each of a region of the third semiconductor region between the second semiconductor region and the second surface and a region of the fifth semiconductor region between the fourth semiconductor region and the second surface. 
 
     
     
       2. The apparatus according to  claim 1 , wherein the same potential is applied to the second semiconductor region and the fourth semiconductor region. 
     
     
       3. The apparatus according to  claim 1 , wherein a voltage applied between the second semiconductor region and the third semiconductor region and a voltage applied between the fourth semiconductor region and the fifth semiconductor region are different. 
     
     
       4. The apparatus according to  claim 1 , wherein the third semiconductor region and the fifth semiconductor region are arranged in regions of different impurity concentrations of the first conductivity type. 
     
     
       5. The apparatus according to  claim 1 , wherein a first transistor is arranged in the second semiconductor region, a second transistor is arranged in the third semiconductor region, a third transistor is arranged in the fourth semiconductor region, and a fourth transistor is arranged in the fifth semiconductor region. 
     
     
       6. The apparatus according to  claim 5 , wherein operation voltages of the first transistor and the third transistor are different. 
     
     
       7. The apparatus according to  claim 1 , wherein the third semiconductor region is neighbored on the fifth semiconductor region. 
     
     
       8. The apparatus according to  claim 1 , further including a sixth semiconductor region of the first conductivity type, which is adjacent to the third semiconductor region. 
     
     
       9. The apparatus according to  claim 8 , further including a seventh semiconductor region of the first conductivity type, which is adjacent to the fifth semiconductor region. 
     
     
       10. The apparatus according to  claim 9 , wherein the impurity concentration of the first conductivity type in the sixth semiconductor region is lower than the impurity concentration of the first conductivity type in the seventh semiconductor region. 
     
     
       11. The apparatus according to  claim 1 , wherein at least one electrode of a collector, an emitter, and a base of a bipolar transistor is arranged in a semiconductor region of the same impurity concentration as the second semiconductor region. 
     
     
       12. A semiconductor apparatus comprising:
 a first semiconductor region including a first surface and a second surface, in which a semiconductor of a first conductivity type is arranged; 
 a second semiconductor region of the first conductivity type, which is arranged between the first surface and the second surface; 
 a third semiconductor region of a second conductivity type, which is arranged in a region between the second semiconductor region and the second surface and on a side portion of the second semiconductor region; 
 a fourth semiconductor region of the first conductivity type, which is arranged between the first surface and the second surface; and 
 a fifth semiconductor region of the second conductivity type, which is arranged in a region between the fourth semiconductor region and the second surface and on a side portion of the fourth semiconductor region, 
 wherein the third semiconductor region and the fifth semiconductor region are separated, and 
 a net impurity concentration of the first conductivity type in the second semiconductor region is lower than a net impurity concentration of the first conductivity type in the fourth semiconductor region. 
 
     
     
       13. A manufacturing method of a semiconductor apparatus, comprising:
 preparing a semiconductor substrate including a first semiconductor region of a first conductivity type; 
 implanting an impurity into a region of the semiconductor substrate where a second semiconductor region of the first conductivity type should be formed; 
 implanting an impurity into a region of a side portion of the second semiconductor region where a third semiconductor region of a second conductivity type should be formed; 
 implanting an impurity into a region of the semiconductor substrate where a fourth semiconductor region of the first conductivity type should be formed; 
 implanting an impurity into a region of a side portion of the fourth semiconductor region where a fifth semiconductor region of the second conductivity type should be formed; and 
 implanting an impurity into a region under the second semiconductor region and the fourth semiconductor region of the first conductivity type where a semiconductor region of the second conductivity type should be formed, 
 wherein an impurity implantation condition is set such that a net impurity concentration of the first conductivity type in the second semiconductor region and the fourth semiconductor region becomes lower than a net impurity concentration of the second conductivity type in the semiconductor region of the second conductivity type under the second semiconductor region and the semiconductor region of the second conductivity type under the fourth semiconductor region. 
 
     
     
       14. The method according to  claim 13 , wherein the impurity implantation condition is set such that the net impurity concentration of the first conductivity type in the second semiconductor region becomes lower than the net impurity concentration of the first conductivity type in the fourth semiconductor region. 
     
     
       15. The method according to  claim 13 , wherein
 a semiconductor region that becomes at least one electrode of a collector, an emitter, and a base of a bipolar transistor is formed when forming the second semiconductor region.