Structure for capacitor protection, package structure, and method of forming package structure

Abstract

A package structure includes: a substrate; a chip arranged on a part of a surface of the substrate; a metal thermal conducting layer arranged on a top surface of the chip; a capacitive structure arranged on another part of the surface of the substrate and arranged to be independent from the chip; and a cover including a first cover layer and a second cover layer connected to the first cover layer. A first opening is defined to extend through the first and the second cover layers. The second cover layer is arranged on a bottom of the first cover layer and perpendicular to the first cover layer. The first cover layer is arranged on the capacitive structure. The chip is received in the first opening. The second cover layer is arranged between the capacitive structure and the chip, and is fixed to the substrate.

What is claimed is: 
     
       1. A structure for capacitor protection, comprising:
 a substrate; 
 a chip, arranged to cover a part of a surface of the substrate; 
 a metal thermal conducting layer, arranged on a top surface of the chip; 
 a capacitive structure, arranged on another part of the surface of the substrate, wherein the another part of the surface of the substrate is not covered by the chip, and the capacitive structure is arranged to be independent from the chip; and 
 a cover, comprising a first cover layer and a second cover layer connected to the first cover layer, wherein the first cover layer defines a first opening extending through the first cover layer, the second cover layer is arranged on a bottom of the first cover layer and perpendicular to the first cover layer, the first opening is further defined to extend through the second cover layer, the first cover layer is arranged on the capacitive structure, the chip is received in the first opening, and the second cover layer is arranged between the capacitive structure and the chip and is fixed to the substrate; and 
 a heat dissipating cover and a connection layer, wherein the heat dissipating cover is arranged on the substrate, the heat dissipating cover comprises a side cover and a top cover connected to the side cover, and the side cover and the top cover cooperatively define a cavity to receive the chip, the metal thermal conducting layer, the capacitive structure, and the cover; and the connection layer is arranged on an edged region of the surface of the substrate and arranged to fix the heat dissipating cover to the substrate, 
 wherein an orthographic projection of the first cover layer onto the surface of the substrate completely covers an orthographic projection of the capacitive structure onto the surface of the substrate. 
 
     
     
       2. The structure for capacitor protection according to  claim 1 , wherein the cover is made of glass, rubber, plastics, or resin. 
     
     
       3. The structure for capacitor protection according to  claim 1 , wherein the cover is made of metal, and a surface of the cover is arranged with an insulation-isolation layer. 
     
     
       4. The structure for capacitor protection according to  claim 1 , wherein
 a projection of the chip onto the surface of the substrate is rectangular or squared, the projection of the chip onto the surface of the substrate has a first chip edge and a second chip edge, and the first chip edge is perpendicular to the second chip edge; 
 a projection of the first cover layer onto the surface of the substrate is a rectangular ring or a squared ring, the projection of the first cover layer onto the surface of the substrate has an inner ring and an outer ring, the inner ring has a first inner edge of the cover and a second inner edge of the cover, the first inner edge is perpendicular to the second inner edge, the outer ring has a first outer edge of the cover and a second outer edge of the cover, and the first outer edge is perpendicular to the second outer edge; 
 a projection of the capacitive structure onto the surface of the substrate is rectangular or squared, the capacitive structure onto the surface of the substrate has a first capacitive structure edge and a second capacitive structure edge; 
 the first capacitive structure edge, the first outer edge of the cover, the first inner edge of the cover, and the first chip edge are parallel with each other, and the second capacitive structure edge, the second outer edge of the cover, the second inner edge of the cover, and the second chip edge are parallel with each other; 
 a length of the first inner edge of the cover is equal to a sum of a length of the first chip edge and 2 times of a first position error, a length of the second inner edge of the cover is equal to a sum of a length of the second chip edge and 2 times of a second position error, a length of the first outer edge of the cover is equal to a sum of the length of the first chip edge, the length of the first capacitive structure edge, and 2 times of the first position error, and the length of the first capacitive edge is equal to a sum of the length of the second chip edge, the length of the second capacitive structure edge, and 2 times of the second position error, and 
 the first position error is 0.03 mm to 0.05 mm, and the second position error is 0.03 mm to 0.05 mm. 
 
     
     
       5. The structure for capacitor protection according to  claim 1 , wherein a distance between the first cover layer and a top surface of the capacitive structure is greater than a third position error, and the third position error is 0.05 mm to 0.1 mm. 
     
     
       6. The structure for capacitor protection according to  claim 1 , wherein a distance between a top surface of the first cover layer and the substrate is smaller than a distance between a top surface of the metal thermal conducting layer and the substrate. 
     
     
       7. The structure for capacitor protection according to  claim 1 , further comprising a sealing layer, arranged between a bottom of the second cover layer and the substrate. 
     
     
       8. The structure for capacitor protection according to  claim 7 , wherein a width of the sealing layer is smaller than a first position error, and the first position error is 0.03 mm to 0.05 mm. 
     
     
       9. A package structure, comprising:
 a substrate; 
 a chip, arranged to cover a part of a surface of the substrate; 
 a metal thermal conducting layer, arranged on a top surface of the chip; 
 a capacitive structure, arranged on another part of the surface of the substrate, wherein the another part of the surface of the substrate is not covered by the chip, and the capacitive structure is arranged to be independent from the chip; 
 a cover, comprising a first cover layer and a second cover layer connected to the first cover layer, wherein the first cover layer defines a first opening extending through the first cover layer, the second cover layer is arranged on a bottom of the first cover layer and perpendicular to the first cover layer, the first opening is further defined to extend through the second cover layer, the first cover layer is arranged on the capacitive structure, the chip is received in the first opening, and the second cover layer is arranged between the capacitive structure and the chip and is fixed to the substrate; and 
 a heat dissipating cover and a connection laver, wherein the heat dissipating cover is arranged on the substrate, the heat dissipating cover comprises a side cover and a top cover connected to the side cover, and the side cover and the top cover cooperatively define a cavity to receive the chip, the metal thermal conducting laver, the capacitive structure, and the cover; and the connection layer is arranged on an edged region of the surface of the substrate and arranged to fix the heat dissipating cover to the substrate. 
 
     
     
       10. The package structure according to  claim 9 , wherein the cover is made of glass, rubber, plastics, or resin. 
     
     
       11. The package structure according to  claim 9 , wherein the cover is made of metal, and a surface of the cover is arranged with an insulation-isolation layer. 
     
     
       12. The package structure according to  claim 9 , wherein
 a projection of the chip onto the surface of the substrate is rectangular or squared, the projection of the chip onto the surface of the substrate has a first chip edge and a second chip edge, and the first chip edge is perpendicular to the second chip edge; 
 a projection of the first cover layer onto the surface of the substrate is a rectangular ring or a squared ring, the projection of the first cover layer onto the surface of the substrate has an inner ring and an outer ring, the inner ring has a first inner edge of the cover and a second inner edge of the cover, the first inner edge is perpendicular to the second inner edge, the outer ring has a first outer edge of the cover and a second outer edge of the cover, and the first outer edge is perpendicular to the second outer edge; 
 a projection of the capacitive structure onto the surface of the substrate is rectangular or squared, the capacitive structure onto the surface of the substrate has a first capacitive structure edge and a second capacitive structure edge; and 
 the first capacitive structure edge, the first outer edge of the cover, the first inner edge of the cover, and the first chip edge are parallel with each other, and the second capacitive structure edge, the second outer edge of the cover, the second inner edge of the cover, and the second chip edge are parallel with each other. 
 
     
     
       13. The package structure according to  claim 12 , wherein
 a length of the first inner edge of the cover is equal to a sum of a length of the first chip edge and 2 times of a first position error, a length of the second inner edge of the cover is equal to a sum of a length of the second chip edge and 2 times of a second position error, a length of the first outer edge of the cover is equal to a sum of the length of the first chip edge, the length of the first capacitive structure edge, and 2 times of the first position error, and the length of the first capacitive edge is equal to a sum of the length of the second chip edge, the length of the second capacitive structure edge, and 2 times of the second position error; and 
 the first position error is 0.03 mm to 0.05 mm, and the second position error is 0.03 mm to 0.05 mm. 
 
     
     
       14. The package structure according to  claim 9 , wherein a distance between the first cover layer and a top surface of the capacitive structure is greater than a third position error, and the third position error is 0.05 mm to 0.1 mm. 
     
     
       15. The package structure according to  claim 9 , wherein
 a distance between a top surface of the first cover layer and a top inner surface of the heat dissipating cover is greater than a distance between a top surface of the metal thermal conducting layer and the a top inner surface of the heat dissipating cover. 
 
     
     
       16. The package structure according to  claim 9 , further comprising a sealing layer, arranged between a bottom of the second cover layer and the substrate. 
     
     
       17. The package structure according to  claim 16 , wherein a width of the sealing layer is smaller than a first position error, and the first position error is 0.03 mm to 0.05 mm. 
     
     
       18. The package structure according to  claim 9 , wherein
 a top inner surface of the dissipating cover is arranged to contact the metal thermal conducting layer allowing heat generated in an inside of the package structure to be spread to an outside; and 
 a plurality of air vents are defined between the heat dissipating cover and the substrate. 
 
     
     
       19. A method of forming a package structure, comprising:
 providing a substrate, Wherein a part of a surface of the substrate is covered by a chip, another part of the surface of the substrate, which is not covered by the chip, is covered by a capacitive structure, and the capacitive structure and the chip are independent from each other; 
 providing a cover, wherein the cover comprises a first cover layer and a second cover layer connected to the first cover layer, the first cover layer defines a first opening extending through the first cover layer, the second cover layer is arranged at a bottom of the first cover layer and perpendicular to the first cover layer, and the first opening further extends through the second cover; 
 arranging the cover on the substrate, wherein the first cover layer is arranged on the capacitive structure, the chip is received in the first opening, and the second cover layer is arranged between the capacitive structure and the chip, and is fixed to the substrate; 
 after arranging the cover on the substrate, forming a metal thermal conducting layer on a top surface of the chip; and 
 after forming the metal thermal conducting layer, performing high-temperature reflow soldering, wherein a temperature set during the high-temperature reflow soldering is greater than a melting point of the metal thermal conducting layer, 
 wherein the method further comprises: 
 arranging a heat dissipating cover and a connection layer, wherein the heat dissipating cover is arranged on the substrate, the heat dissipating cover comprises a side cover and a top cover connected to the side cover, and the side cover and the top cover cooperatively define a cavity to receive the chip, the metal thermal conducting layer, the capacitive structure, and the cover; and the connection layer is arranged on an edged region of the surface of the substrate and arranged to fix the heat dissipating cover to the substrate. 
 
     
     
       20. The method of forming a package structure according to  claim 19 , wherein
 the performing the high-temperature reflow soldering comprises performing a first high-temperature reflow soldering and performing a second high-temperature reflow soldering; and 
 after arranging the heat dissipating cover on the substrate, t method further comprises: 
 performing the first high-temperature reflow soldering to solder the heat dissipating cover, the chip, and the metal thermal conducting layer together; and 
 after the performing the first high-temperature reflow soldering, performing the second high-temperature reflow soldering to solder a soldering ball to a bottom of the substrate.