Signal-to-noise and interference ratio (SNAIR) aware analog to digital converter (ADC)-based receiver and a method thereof

Abstract

A signal-to-noise and interference ratio (SNAIR) aware analog to digital converter (ADC)-based receiver and a method thereof is disclosed. The SNAIR aware-ADC based receiver comprises an analog front end (AFE) configured for recovering an input data signal with a bit error rate (BER) below a target BER. The SNAIR aware-ADC based receiver further comprises a sampler communicatively coupled to the AFE. A DSP unit is communicatively coupled to the SADC array. The DSP unit comprises a feed forward equalizer (FFE) configured to remove residual inter-symbol interference (ISI) by multiplying a delayed version of the digital data signal with Htap values. The CDR system is configured to process the generated plurality of error signals and data signals. An eye quality measurement system is communicatively coupled to an output of the DSP unit. A digital control communicatively coupled to each of the AFE, the sampler, the SADC array, the DSP unit, and the eye quality measurement system.

The invention claimed is: 
     
       1. A Signal to Noise And Interference Ratio (SNAIR) aware-Analog to Digital Converter (ADC)-based-receiver, wherein the SNAIR aware-ADC based receiver comprises:
 an analog front end (AFE) configured for recovering an input data signal with a bit error rate (BER) below a target BER; 
 a sampler communicatively coupled to the AFE, wherein the sampler is configured for receiving the input data signal from the AFE, sampling the received input data signal, and distributing the sampled input data signal to a sub-analog-to-digital converter (SADC) array; 
 the SADC array communicatively coupled to the sampler, and wherein the SADC array comprises an array of identical analog-to-digital converters (ADCs) configured for converting the sampled input data signal into a digital data signal, and wherein the ADCs are time-interleaved for achieving a predetermined sampling frequency; 
 a digital signal processing (DSP) unit communicatively coupled to the SADC array, wherein the DSP unit uses a baud rate sampling scheme, and wherein the DSP unit comprises: 
 a feed forward equalizer (FFE) configured to remove residual inter-symbol interference (ISI) by multiplying a delayed version of the digital data signal with Htap values; and 
 one or more-taps decision feedback equalizer (DFE) configured to remove remaining ISI caused by a first y previous symbols where y is the number of DFE taps using (n−1) decision levels at each of ‘n’ possible previous symbols, where n is the number of levels used in a PAM scheme; 
 a baud rate sampling system communicatively coupled to the DSP unit, wherein the baud rate sampling system is configured to generate a plurality of error signals and data signals using an output of the one or more-taps decision feedback equalizer (DFE); 
 a clock data recovery (CDR) system communicatively coupled to the baud rate sampling system, wherein the CDR system is configured to process the generated plurality of error signals and data signals for aligning a main sample clock with the input data signal and maximize a corresponding eye opening; 
 an eye quality measurement system communicatively coupled to an output of the DSP unit, wherein the eye quality measurement system is configured to measure an eye quality of the input data signal by determining a margin estimation value and corresponding outer eye measurements associated with an eye; and 
 a digital control communicatively coupled to each of the AFE, the sampler, the SADC array, the DSP unit, and the eye quality measurement system, wherein the digital control is operated by instructions from the DSP unit and is configured for:
 auto-calibrating each of the AFE, the sampler, the SADC array, and the eye quality measurement system; and 
 optimizing performance of the AFE to recover the input data signal at the target BER. 
 
 
     
     
       2. The SNAIR aware-ADC based-receiver of  claim 1 , responsive to removing the ISI caused by the first previous y previous symbols where y is the number of DFE taps using the (n−1) decision levels at each of ‘n’ possible previous symbols, wherein n is the number of levels used in a PAM scheme, the one or more taps DFE is configured to:
 predetermine the ISI caused due to the first previous symbol; and 
 determine a final data value based on the previous symbol decision d(n−1) and a current raw ADC output value is used to calculate d(n), where n is a number of symbols. 
 
     
     
       3. The SNAIR aware-ADC based-receiver of  claim 1 , wherein the baud rate sampling system is further configured to:
 de-multiplex one or more comparator outputs such that a data sample and an error sample are generated for each symbol of the input data signal by utilising a previous symbol decision; and 
 generate the plurality of error signals by re-using at least one of a set of predetermined unused decisions along with a d(n−1)*h 1  value, wherein the plurality of error signals are generated for a maximum number of possible transitions in the input data signal. 
 
     
     
       4. The SNAIR aware-ADC based-receiver of  claim 1 , wherein the AFE comprises:
 a matching network configured for controlling a differential input impedance as compared to a predetermined value; 
 an attenuator communicatively coupled to an output of the matching network, wherein the attenuator is configured for attenuating the input data signal into a predetermined range to ensure linearity of the input data signal, and wherein an amount of attenuation is dependent upon a predetermined signal-swing value, and wherein the amount of attenuation is calibrated at a link start-up using the DSP unit; 
 a long tail equalizer (LTE) communicatively coupled to an output of the attenuator, wherein the LTE is configured to equalize low-frequency content in the input data signal and generate a long tail in a pulse response of the input data signal, and wherein the LTE is calibrated at the link start-up and in a mission mode using the DSP unit; 
 a continuous time linear equalizer (CTLE) communicatively coupled to an output of the LTE, wherein the CTLE is configured to attenuate low frequency content of the input data signal between a direct current and a maximum frequency content of the input data signal, and wherein the CTLE is auto-calibrated using the DSP unit; and 
 a variable gain amplifier (VGA) communicatively coupled to an output of the CTLE, wherein the VGA is configured to boost the signal swing value of the input data signal to a level in order for SNAIR to correspond to the target BER. 
 
     
     
       5. The SNAIR aware-ADC based-receiver of  claim 1 , further comprising:
 a phase interpolator (PI) communicatively coupled to the sampler and the CDR system, wherein the PI is configured to rotate an input clock from at least one subset of a set comprising a phase-locked-loop (PLL) and a clock source to a specified phase relationship, and wherein the PI is controlled by a at least first-order loop implemented in the digital control; and 
 a clock generation system communicatively coupled to the SADC array, wherein the clock generation system is configured to generate a specific lower frequency clock signal from a main sample clock derived from the CDR system and the clock source. 
 
     
     
       6. The SNAIR aware-ADC based-receiver of  claim 1 , wherein the DSP unit further comprises:
 a linearity calibration system configured to: 
 determine whether the input data signal at an input of the SADC array comprises a non-linearity condition above a predetermined threshold value; and 
 attenuate a signal swing value of the input data signal in the event that the non-linearity exceeds the predetermined threshold value. 
 
     
     
       7. The SNAIR aware-ADC based-receiver of  claim 1 , wherein the CDR system is further configured to track a phase of the input data signal continuously and determine an optimum sampling time for each received symbol of the input data signal. 
     
     
       8. The SNAIR aware-ADC based-receiver of  claim 1 , wherein the baud rate sampling system uses a baud rate architecture. 
     
     
       9. The SNAIR aware-ADC based-receiver of  claim 1 , wherein the CDR system further comprises:
 a phase detector configured to transform the generated plurality of error signals and data signals into a subset of a set comprising: early votes, late votes, and no votes; 
 a voter configured to aggregate votes output from the phase detector; wherein the voter determines a most common vote amongst the aggregated votes, and wherein the voter forwards the determined most common vote to a first order digital filter; and 
 the at least first order digital filter configured to generate a first input gain for a proportional path and a second input gain for an integral path, wherein an output of the at least first order digital filter is integrated to provide a phase interpolator (PI) code. 
 
     
     
       10. The SNAIR aware-ADC based-receiver of  claim 1 , wherein the CDR system further utilises an independent DFE from a main data path allowing the CDR h 1  to be set independently of a data path h 1  correction. 
     
     
       11. The SNAIR aware-ADC based-receiver of  claim 1 , respondent to measuring the eye quality of the input data signal by determining the margin estimation value and the corresponding outer eye measurements associated with the eye, the eye quality measurement system is further configured to:
 split the input data signal to obtain an up-margin value and a down-margin value for a plurality of sub-eyes; 
 adapt one or more threshold values associated with the up-margin value and the down-margin value, wherein the threshold values are aligned to programmable BER threshold values; 
 determine an upBER value and a downBER value at a sample point corresponding to each of the up-margin values and the down-margin values by extrapolating a probabilities threshold value and adapted threshold values associated with the up-margin value and the down-margin value; and 
 determine the margin estimation value of the eye based on the determined upBER value and the downBER value. 
 
     
     
       12. The SNAIR aware-ADC based-receiver of  claim 1 , wherein the digital control comprises a plurality of subsystems in the form of programmable instructions executable by the DSP unit, and wherein the plurality of subsystems comprises:
 an adaptation subsystem configured to: 
 calibrate each element of the SADC array by determining a gain value and an offset value; 
 perform one or more initial calibrations with initial conditions to components of the AFE; and 
 calibrate a CTLE and a VGA to increase an ability of the CDR system to lock by estimating a breakdown value of a power versus frequency value, wherein the breakdown value of the power versus the frequency value is calculated using a band power measurement subsystem, and wherein upon calculating the power versus frequency value of the sampled data, the CTLE is calibrated until power in each band is related by a programmable target ratio; 
 a CDR locking subsystem configured to lock the CDR system with a set of initial conditions; 
 a tap estimation subsystem configured to adapt the Htap values of the FFE by correlating the generated plurality of error signals and the delayed input data signal, wherein the Htap values are updated with a gain factor for maintaining a calibration-loop stability by using the correlated plurality of error signals and the delayed input data signal; 
 an eye-centering subsystem configured to center a sampling position of the input data signal by modifying a DFE correction value corresponding to the first previous symbol based on a majority of votes of each sub-eye asymmetry signals; and 
 an AFE tuning subsystem configured to tune setting of the AFE to perform at a level corresponding to a level less than or equal to the target BER for recovering the input data signal at the target BER. 
 
     
     
       13. The SNAIR aware-ADC based-receiver of  claim 12 , wherein the CDR locking subsystem is configured to increase an acquisition range of a CDR loop using a higher CDR Proportional (1st order) path gain (Kprop) value, while maintaining CDR loop stability. 
     
     
       14. The SNAIR aware-ADC based-receiver of  claim 12 , wherein the digital control is configured to monitor SNAIR during operation and adapt to a predetermined threshold SNAIR target value for adapting across process, voltage, and temperature (PVT) variations. 
     
     
       15. The SNAIR aware-ADC based-receiver of  claim 12 , wherein the CDR subsystem is configured to align the eye position by adjusting the DFE correction value based on a majority vote of the eye asymmetry signals. 
     
     
       16. The SNAIR aware-ADC based-receiver of  claim 12 , wherein the band power measurement subsystem is configured at a link start-up time to filter the input data signal with a digital high-pass filter and a low-pass filter, wherein results of the high-pass filter are sent to a power measurement block, and wherein the filtered input signal is used to generate a power signal from a Fnyquist/2 to a Fnyquist value, and wherein the Fnyquist value corresponds to a sample rate/2, and wherein results of the low-pass filter are decimated by a factor of two and filtered using a second high- and low-pass filter in a recursive arrangement to measure one or more frequency bands of interest. 
     
     
       17. A method for recovery a signal transmitted over a channel using a signal to noise and interference ratio (SNAIR) aware-analog to digital (ADC)-based-receiver, the method comprising:
 calibrating a sub-analog-to-digital converter (SADC) array for determining a gain value and an offset value for each element and also of an input data signal, wherein the SADC array is comprised of an array of identical analog-to-digital converters (ADCs), and wherein each ADC is configured for converting the input data signal into a digital data signal, and wherein the ADCs are time-interleaved for achieving a predetermined sampling frequency; 
 performing initial calibrations with initial conditions to components of an analog front end (AFE), wherein the components of the AFE are comprised of a matching network, an attenuator, a long tail equalizer (LTE), a continuous time linear equalizer (CTLE), and a variable gain amplifier (VGA); 
 calibrating the CTLE and the VGA to increase an ability of a clock data recovery (CDR) system to lock by estimating a breakdown value of a power versus frequency value, wherein the breakdown value of the power versus the frequency value is estimated using a band power measurement subsystem, and wherein upon estimating the breakdown value of the power versus the frequency value, the CTLE is calibrated until power in each band is at a target ratio nominally equal; 
 locking the CDR system with initial conditions upon calibrating the CTLE and the VGA; 
 
       adapting Htap values of a feed forward equalizer (FFE) by correlating a plurality of error signals and a delayed input data signal, wherein the Htap values are updated with a gain factor for maintaining calibration loop stability by using the correlated plurality of error signals and the delayed input data signal;
 centering an eye position of the input data signal by modifying a pulse response at a unit interval (h 1 ) value based on a majority of votes of each sub-eye asymmetry signals; and 
 tuning settings of the AFE to perform at a level corresponding to at least one of a level equal to a level less than a target bit error rate (BER) for recovering the input data signal at the target BER. 
 
     
     
       18. The method of  claim 17 , wherein locking the CDR system with initial conditions upon calibrating the CTLE and the VGA comprises increasing an acquisition range of the clock data recovery (CDR) during the CDR system lock operation using a higher CDR Proportional (1st order) path gain (Kprop) value, while maintaining the CDR loop stability. 
     
     
       19. The method of  claim 17 , further comprising:
 monitoring a SNAIR during operation; and 
 adapting to a predetermined SNAIR target value for adapting across process, voltage, and temperature (PVT) variations. 
 
     
     
       20. The method of  claim 17 , wherein centering the eye position of the input data signal comprises centering the eye position by adjusting the h 1  value based on a majority vote of the eye asymmetry signals.