Fet construction with copper pillars or bump directly over the fet

Abstract

A method of forming a semiconductor device with a metal pillar overlapping a first top metal interconnect and a second top metal interconnect is disclosed. The metal pillar overlapping the first top metal interconnect and second top metal interconnect is connected to the first top metal interconnect by top metal vias while the second top metal interconnect does not contain top metal vias and remains free of a direct electrical connection to the metal pillar. The metal pillars are attached directly to top metal vias without a bond pad of metal. The elimination of the bond pad layer reduces the mask count, processing, and cost of the device. In addition, the elimination of the bond pad results in reduced die area requirements for the metal pillar.

What is claimed is: 
     
       1. A semiconductor device, comprising:
 a substrate, the substrate including a semiconductor material; 
 a semiconductor component extending into the semiconductor material; 
 an interconnect region over the semiconductor component; 
 a top metal layer in the interconnect region; 
 a protective dielectric layer on the top metal layer; 
 a first top metal interconnect lead in the top metal layer; 
 a second top metal interconnect lead in the top metal layer; 
 top metal vias through the protective dielectric layer, the top metal vias contacting the first top metal interconnect lead; and 
 a metal pillar electrically connected to the top metal vias; 
 wherein:
 the metal pillar extends over a portion of the second top metal interconnect lead; 
 the protective dielectric layer separates the metal pillar from the second top metal interconnect lead; and 
 the semiconductor device is free of a direct electrical connection through the protective dielectric layer from the metal pillar to the second top metal interconnect lead. 
 
 
     
     
       2. The semiconductor device of  claim 1  wherein the metal pillar includes a barrier sublayer under the metal pillar, the barrier sublayer including a material selected from a group consisting of titanium, tantalum, tungsten, titanium nitride, and tantalum nitride. 
     
     
       3. The semiconductor device of  claim 1  wherein the metal pillar includes a material selected from a group consisting of copper and nickel. 
     
     
       4. The semiconductor device of  claim 1  wherein a metal layer electrically connects the top metal vias to the metal pillar, the metal layer including a material selected from a group consisting of copper and aluminum. 
     
     
       5. The semiconductor device of  claim 1 , wherein the metal pillar contains a cap over the metal pillar; the cap including a material selected from a group consisting of tin, zinc, antimony, copper, silver, bismuth, lead, and indium. 
     
     
       6. The semiconductor device of  claim 1 , wherein the protective dielectric layer includes a first sublayer over the top metal layer, and includes a second sublayer on the first sublayer, wherein the first sublayer includes a material selected from a group consisting of silicon dioxide and silicon oxynitride and the second sublayer includes a material selected from a group consisting of silicon oxynitride and silicon nitride. 
     
     
       7. The semiconductor device of  claim 1 , wherein the protective dielectric layer includes a dielectric material selected from a group consisting of silicon oxynitride and silicon nitride. 
     
     
       8. The semiconductor device of  claim 1 , wherein the protective dielectric layer includes an etch stop sublayer over the top metal layer. 
     
     
       9. The semiconductor device of  claim 1 , wherein the first top metal interconnect lead includes a first segment and a second segment with the second top metal interconnect lead located between the first segment and the second segment and wherein a first subset of top metal vias connect between the metal pillar and the first segment and a second subset of top metal vias connect between the metal pillar and the second segment. 
     
     
       10. A method of forming a semiconductor device, comprising:
 forming a semiconductor device extending into a semiconductor material of a device substrate; 
 forming an interconnect region on the semiconductor device, the interconnect region including a top metal layer; 
 forming a first top metal interconnect lead in the top metal layer and a second top metal interconnect lead in the top metal layer adjacent to the first top metal interconnect lead; 
 forming a protective dielectric layer on the top metal layer; 
 removing the protective dielectric layer in a top via openings in the protective dielectric layer to expose a portion of the first top metal interconnect lead; 
 forming top metal vias in the top via openings contacting the first top metal interconnect lead; and 
 forming a metal pillar on the top metal vias; 
 
       wherein:
 the metal pillar extends over a portion of the second top metal interconnect lead; 
 the protective dielectric layer separates the metal pillar from the second top metal interconnect lead; and 
 the semiconductor device is free of a direct electrical connection through the protective dielectric layer from the metal pillar to the second top metal interconnect lead. 
 
     
     
       11. The method of  claim 10 , wherein forming a metal pillar includes forming a barrier sublayer on the metal pillar, the barrier sublayer including a material selected from a group consisting of titanium, tantalum, tungsten, titanium nitride, and tantalum nitride. 
     
     
       12. The method of  claim 10 , wherein forming the metal pillar includes a material selected from a group consisting of copper and nickel. 
     
     
       13. The method of  claim 10 , wherein forming a metal pillar cap over the metal pillar includes a material selected from a group consisting of tin, zinc, antimony, copper, silver, bismuth, lead, and indium. 
     
     
       14. The method of  claim 10 , wherein forming the protective dielectric layer includes forming a first sublayer over the top metal layer, and includes forming a second sublayer on the first sublayer, wherein the first sublayer includes a material selected from a group consisting of silicon dioxide and silicon oxynitride and the second sublayer includes a material selected from a group consisting of silicon oxynitride and silicon nitride. 
     
     
       15. The method of  claim 10 , wherein forming the protective dielectric layer includes forming a layer of a dielectric material selected from a group consisting of silicon oxynitride and silicon nitride. 
     
     
       16. The method of  claim 10 , wherein forming the protective dielectric layer includes forming a stress relief layer over the top metal layer and removing the stress relief layer in areas which exposes top metal vias. 
     
     
       17. The method of  claim 10 , further comprising forming a stress relief layer on top of the protective dielectric layer, the stress relief layer including a material selected from polyimide or n-polybenzoxazole. 
     
     
       18. The method of  claim 10 , wherein forming the metal pillar includes forming an under metal pillar metal layer which includes a material selected from a group consisting of copper and aluminum. 
     
     
       19. The method of  claim 10 , wherein forming the first top metal interconnect lead includes forming a first segment and a second segment with the second top metal interconnect lead located between the first segment and the second segment and wherein forming the top metal vias includes forming a first subset of top metal vias that connect between the metal pillar and the first segment and forming a second subset of top metal vias connect between the metal pillar and the second segment. 
     
     
       20. A semiconductor device, comprising:
 an interconnect region over a device substrate; 
 a top metal layer in the interconnect region; 
 a protective dielectric layer on the top metal layer; 
 a first top metal interconnect lead in the top metal layer; 
 a second top metal interconnect lead in the top metal layer; 
 a via level including first top metal vias through the protective dielectric layer and second top metal vias through the protective dielectric layer, the first top metal vias contacting the first top metal interconnect lead and the second top metal vias contacting the second top metal interconnect lead; and 
 a first metal pillar on the first top metal vias and a second metal pillar on the second top metal vias; 
 wherein: 
 the first metal pillar extends over a portion of the second top metal interconnect lead and the second metal pillar extends over a portion of the first top metal interconnect lead; 
 the protective dielectric layer separates the first metal pillar from the second top metal interconnect lead and the second metal pillar from the first top metal interconnect lead; and 
 the via level includes no vias between the first metal pillar and the second top metal interconnect lead and no vias between the second metal pillar and the first top metal interconnect. 
 
     
     
       21. The semiconductor device of  claim 20 , wherein the first top metal interconnect lead includes a first segment and a second segment with the second top metal interconnect lead located between the first segment and the second segment and wherein a first subset of first top metal vias connect between the first metal pillar and the first segment and a second subset of first top metal vias connect between the first metal pillar and the second segment.