Voltage level multiplier module for multilevel power converters

Abstract

Generalized circuit topology of voltage level multiplier modules (VLMMs) for use with multilevel inverters (MLIs) and power converter circuits comprising at least one VLMM and a MLI are described herein. The VLMM is configured to receive a first output voltage from the MLI having a first number of voltage levels and to generate a second output voltage having a second number of voltage levels. If the first number of voltage levels is M, and the VLMM is N-fold voltage level multiplier, then second number of voltage levels is M×N+1. Switching pattern generators for use with the VLMM and modulation methods for controlling switching elements of the VLMM are also described herein.

What is claimed is: 
     
       1. A power converter circuit, comprising:
 a multilevel inverter providing at an output thereof a first output voltage having M voltage levels; and 
 at least one N-fold voltage level multiplier module electrically connected to the output of the multilevel inverter and comprising a plurality of circuit elements configured to provide at least five voltage levels, the at least one voltage level multiplier module configured to receive the first output voltage from the multilevel inverter and to generate a second output voltage having M×N+1 voltage levels, where N is at least four. 
 
     
     
       2. The power converter circuit of  claim 1 , wherein the multilevel inverter is configured to provide three output voltages, each of the three output voltages being phase shifted by 2π/3 and having the M voltage levels, three of the at least one voltage level multiplier module being connected to receive a respective one of the three output voltages and being configured to each generate the second output voltage at a corresponding phase. 
     
     
       3. The power converter circuit of  claim 1 , further comprising an output filter connected to an output of the voltage level multiplier module, the output filter comprising an inductor and a capacitor, wherein the inductor has an inductance value of 
       
         
           
             
               L 
               = 
               
                 
                   V 
                   DC 
                 
                 
                   8 
                   × 
                   
                     ( 
                     
                       n 
                       - 
                       1 
                     
                     ) 
                   
                   × 
                   Δ 
                   ⁢ 
                   
                       
                   
                   ⁢ 
                   
                     I 
                     L 
                   
                   × 
                   
                     f 
                     
                       1 
                       ⁢ 
                       st 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       SW 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       Harmonic 
                     
                   
                 
               
             
           
         
       
       and the capacitor has a capacitance value of 
       
         
           
             
               
                 C 
                 = 
                 
                   4 
                   
                     
                       
                         ( 
                         
                           2 
                           ⁢ 
                           π 
                           × 
                           
                             f 
                             
                               1 
                               ⁢ 
                               st 
                               ⁢ 
                               
                                   
                               
                               ⁢ 
                               SW 
                               ⁢ 
                               
                                   
                               
                               ⁢ 
                               Harmonic 
                             
                           
                         
                         ) 
                       
                       2 
                     
                     × 
                     L 
                   
                 
               
               , 
             
           
         
       
       where n is the number of output voltage levels, ΔI L  is the desired output current ripple, f 1st SW Harmonic  is the first switching harmonic cluster frequency and V DC  is the DC-link voltage. 
     
     
       4. The power converter circuit of  claim 1 , further comprising a controller having:
 a processor and non-transitory memory storing instructions to cause the processor to perform:
 generating a first reference signal having staircase voltage levels based on level detection of a sinusoidal input reference signal; 
 generating a second reference signal by subtracting the first reference signal from the sinusoidal input reference signal; and 
 
 one of:
 comparator circuitry for comparing the second reference signal to a plurality of triangular carrier signals to generate a plurality of switching signals for the voltage level multiplier module, each of the plurality of switching signals for controlling a given one of a plurality of switching elements of the at least one voltage level multiplier module; and 
 further instructions stored in said memory for causing the processor to further perform comparing the second reference signal to a plurality of triangular carrier signals to generate a plurality of switching signals for the voltage level multiplier module, each of the plurality of switching signals for controlling a given one of the plurality of switching elements of the at least one voltage level multiplier module. 
 
 
     
     
       5. A power converter circuit, comprising:
 a multilevel inverter providing at an output thereof a first output voltage having M voltage levels; and 
 at least one N-fold voltage level multiplier module electrically connected to the output of the multilevel inverter and comprising a plurality of switching elements, 
 wherein said at least one N-fold voltage level multiplier module provides at least five voltage levels, receives the first output voltage from the multilevel inverter and generates a second output voltage having M×N+1 voltage levels, where N is at least four. 
 
     
     
       6. The voltage level multiplier module of  claim 5 , wherein the voltage level multiplier module is connectable in series and is adapted to generate a converter output voltage of M×N m +Σ k=0   m-1 N k  voltage levels, where k is an index of each of the series-connected voltage level multiplier modules ranging from 1 to m and m is the number of series-connected voltage level multiplier modules. 
     
     
       7. The voltage level multiplier module of  claim 6 , wherein the multilevel inverter comprises a first power source operating at a DC voltage level E and wherein the plurality of switching elements comprise an additional power source operating at a voltage level of E/(N (k-1) ×(M−1)), for each k th  series-connected voltage level multiplier module. 
     
     
       8. The voltage level multiplier module of  claim 6 , wherein the plurality of switching elements comprise two low frequency switches operating at the E/(N (k-1) ×(M−1)) voltage level, for each k th  series-connected voltage level multiplier module. 
     
     
       9. The voltage level multiplier module of  claim 8 , wherein the plurality of switching elements comprise 2×n high frequency switches and n−1 capacitors each having a capacitor voltage of ((n−b)×E)/n×N (k-1) ×(M−1)) where b is an index of each of the n−1 capacitors, b ranging from 1 to n−1, the high frequency switches operating at a voltage of E/(n×N (k-1) ×(M−1)), for each k th  series-connected voltage level multiplier module. 
     
     
       10. The voltage level multiplier module of  claim 9 , wherein the two low frequency switches and the 2×n high frequency switches are controlled to provide sensor-less voltage balancing to the n−1 capacitors. 
     
     
       11. The voltage level multiplier module of  claim 5  wherein said instructions cause the processor to control a given one of the plurality of switching elements based on phase disposition pulse width modulation. 
     
     
       12. The switching pattern generator of  claim 11 , configured to generate the plurality of switching signals based on comparing a reference voltage signal to a group of triangular carrier signals. 
     
     
       13. The switching pattern generator of  claim 12 , wherein the plurality of switching elements comprise 2×n high frequency switches and n−1 capacitors and wherein the group of triangular carrier signals are n phase-shifted triangular carrier signals that are shifted by 2×π/n. 
     
     
       14. The switching pattern generator of  claim 13 , wherein the plurality of switching signals provide sensor-less voltage balancing to the n−1 capacitors. 
     
     
       15. A method for controlling a plurality of switching elements of a voltage level multiplier module configured to provide at least five voltage levels, the method comprising:
 generating a first reference signal having staircase voltage levels based on level detection of a sinusoidal input reference signal; 
 generating a second reference signal by subtracting the first reference signal from the sinusoidal input reference signal; 
 comparing the second reference signal to a plurality of triangular carrier signals to generate comparison results; 
 processing the comparison results to generate a plurality of switching signals; and 
 providing the plurality of switching signals to the voltage level multiplier module, each of the plurality of switching signals for controlling a given one of the plurality of switching elements. 
 
     
     
       16. The method of  claim 15  wherein the plurality of triangular carrier signals are phase-shifted triangular carrier signals. 
     
     
       17. The method of  claim 16  wherein the plurality of triangular carrier signals are n triangular carrier signals that are shifted by 2π/n, where the plurality of circuit elements comprise 2×n high frequency switches and n−1 capacitors. 
     
     
       18. The method of  claim 15  further comprising comparing the second reference signal to a zero value by applying a zero-crossing comparator to generate comparison results for two low-frequency switching elements of the plurality of circuit elements. 
     
     
       19. The method of  claim 15  further comprising sensor-less balancing a voltage of n−1 capacitors according to the switching signals, where the plurality of circuit elements comprise n−1 capacitors.