Clock synchronization using wireless side channel

Abstract

Individual clock adjustments between electronic devices are typically based around a round-trip time (RTT) measurement of the reference message between initiating and the receiving devices. With increasing expectations of clock synchronization accuracy, as well as widespread use of wireless data networks, the presently disclosed technology provides a dedicated clock synchronization network that yields a fixed delay between hops and within associated devices of a dedicated clock synchronization network. By accounting for the known delays between hops and within associated devices of the dedicated clock synchronization network, better clock synchronization accuracy can be achieved than prior art techniques that estimate latency based on an RTT measurement.

What is claimed is: 
     
       1. A method for synchronizing a slave device to a master device comprising:
 generating a master timing reference using master timing circuitry; 
 transmitting the master timing reference from the master device outbound over a dedicated data channel; 
 receiving the master timing reference with a constant delay from the master device to the slave device over the dedicated data channel; and 
 synchronizing a slave timing reference of the slave device to the master timing reference using the constant delay over the dedicated data channel using a snapshot of the master timing reference transmitted over the dedicated data channel and a fixed known delay for a data packet containing the snapshot to be transmitted between the master device and the slave device. 
 
     
     
       2. The method of  claim 1 , wherein the dedicated data channel is a wireless connection between the master device and the slave device. 
     
     
       3. A method for synchronizing a slave device to a master device comprising:
 generating a master timing reference using master timing circuitry; 
 transmitting the master timing reference from the master device outbound over a dedicated data channel; 
 receiving the master timing reference with a constant delay from the master device to the slave device over the dedicated data channel; and 
 synchronizing a slave timing reference of the slave device to the master timing reference using the constant delay over the dedicated data channel using a known packet rate of a series of incoming packets from the master device containing the master timing reference. 
 
     
     
       4. A wireless clock synchronization network comprising:
 a master device including:
 master timing circuitry configured to generate a master timing reference; and 
 a wireless radio transmitter configured to transmit the master timing reference with a fixed known delay on a dedicated wireless data channel; 
 
 a slave device including:
 a wireless radio receiver configured to receive the master timing reference on the dedicated wireless data channel; and 
 slave timing circuitry configured to synchronize a slave timing reference to the master timing reference with a correction factor based on the fixed known delay. 
 
 
     
     
       5. A clock synchronization network comprising:
 a master device including:
 master timing circuitry configured to generate a master timing reference; and 
 a data output configured to transmit the master timing reference on a dedicated data channel; and 
 
 a slave device including:
 a data input configured to receive the master timing reference on the dedicated data channel; and 
 slave timing circuitry configured to synchronize a slave timing reference to the master timing reference using a constant delay over the dedicated data channel, wherein the slave timing circuitry synchronizes the slave timing reference to the master timing reference using a known packet rate of a series of incoming packets over the dedicated channel from the master device containing the master timing reference. 
 
 
     
     
       6. A clock synchronization network comprising:
 a master device including:
 master timing circuitry configured to generate a master timing reference; and 
 a data output configured to transmit the master timing reference on a dedicated data channel; and 
 
 a slave device including:
 a data input configured to receive the master timing reference on the dedicated data channel; and 
 slave timing circuitry configured to synchronize a slave timing reference to the master timing reference using a constant delay over the dedicated data channel, wherein the slave timing circuitry synchronizes the slave timing reference to the master timing reference using a snapshot of the master timing reference transmitted over the dedicated data channel and a fixed known delay for a data packet containing the snapshot to be transmitted between the master device and the slave device. 
 
 
     
     
       7. The clock synchronization network of  claim 6 , wherein the master timing circuitry includes an oscillator that serves as a reference for a timer that generates the master timing reference. 
     
     
       8. The clock synchronization network of  claim 6 , wherein the slave timing circuitry includes an oscillator that serves as a reference for a timer that generates the slave timing reference, and wherein the slave timing circuitry is to synchronize the slave timing reference by adjusting an oscillator count for toggling the slave timing reference. 
     
     
       9. The clock synchronization network of  claim 6 , wherein the constant delay includes delays at one or more of: the master device, the slave device, and the dedicated data channel. 
     
     
       10. The clock synchronization network of  claim 6 , wherein the slave timing reference is synchronized to the master timing reference without a round-trip time (RTT) measurement. 
     
     
       11. The clock synchronization network of  claim 6 , wherein the dedicated data channel is a direct wireless connection between the master device and the slave device. 
     
     
       12. The clock synchronization network of  claim 6 , wherein the dedicated data channel is a wired connection between the master device and the slave device. 
     
     
       13. The clock synchronization network of  claim 6 , further comprising:
 a second slave device including:
 a data input to receive the master timing reference on the dedicated data channel from the slave device; and 
 slave timing circuitry to synchronize a second slave timing reference to the master timing reference with a correction factor based on the constant delay over the dedicated data channel and a number of hops from the master device to the second slave device. 
 
 
     
     
       14. The clock synchronization network of  claim 6 , wherein the master device is a component of an autonomous car and the slave device is a sensor on the autonomous car. 
     
     
       15. The clock synchronization network of  claim 6 , wherein the master device and the slave device are each one or both of audio and video devices. 
     
     
       16. The clock synchronization network of  claim 6 , wherein precision of synchronization of the slave timing reference to the master timing reference is within one time tick. 
     
     
       17. The clock synchronization network of  claim 6 , wherein the master timing reference is generated by an application executing on the master device. 
     
     
       18. The clock synchronization network of  claim 17 , wherein the master timing reference is generated at a rate that is based on a desired precision of an application executing on the slave device.