Semiconductor structure with partially embedded insulation region and related method

Abstract

A technique to make silicon oxide regions from porous silicon and related semiconductor structures is disclosed. The porous silicon is made in situ by anodizing P doped silicon regions. Thus, the shape and profile of the oxide regions may be controlled by controlling the shape and profile of the P doped silicon regions.

The invention claimed is: 
     
       1. A method, comprising:
 forming a first P doped region within a substrate; 
 forming a first N doped region at least partially in the first P doped region; 
 forming porous silicon in the first P doped region by anodizing the first P doped region; 
 forming a first silicon oxide region by oxidizing the porous silicon in the P doped region; and 
 forming a second P doped region within the first N doped region. 
 
     
     
       2. The method of  claim 1 , further comprising forming an NMOS transistor in the second P doped region and forming a PMOS transistor adjacent to the NMOS transistor and within the first N doped region. 
     
     
       3. The method of  claim 1 , further comprising:
 forming a third P doped region in the first N doped region, the third P doped region including a first side and a second side; 
 forming a second N doped region and a third N dope region by counter-doping the third P doped region, each of the second N doped region and the third N doped region partially overlaying the third P doped region and having a side exposed from the third P doped region, the second N doped region and the third N doped region being separated from one another by the third P doped region; 
 forming porous silicon in the third P doped region by anodizing the third P doped region; and 
 forming a second silicon oxide region by oxidizing the porous silicon in the third P doped region. 
 
     
     
       4. The method of  claim 3 , further comprising forming a fourth P doped region adjacent to the second N doped region, the third N doped region and a remaining part of the third P doped region. 
     
     
       5. The method of  claim 1  wherein the anodizing the first P doped region includes applying an electrical field on the first P doped region. 
     
     
       6. The method of  claim 1 , further comprising forming a resistor device within the first N doped region. 
     
     
       7. The method of  claim 6  wherein the forming the resistor device includes forming a plurality of resistor devices within the first N doped region. 
     
     
       8. The method of  claim 7 , further comprising forming an interconnection to couple the plurality of resistor devices in series. 
     
     
       9. The method of  claim 1 , wherein the first silicon oxide region at least partially surrounds a first sidewall of the first N doped region. 
     
     
       10. A method, comprising:
 forming, by doping, a first P doped silicon region within a first N type silicon region of a substrate; 
 forming, by counter-doping, a second N type silicon region over the first P doped silicon region, the second N type silicon region at least partially within the first P doped silicon region, the first P doped silicon region adjacent to a first surface of the second N type silicon region and at least partially surrounding a sidewall of the second N type silicon region; 
 forming porous silicon in the first P doped silicon region by anodizing the first P doped silicon region; and 
 forming a first silicon oxide region by oxidizing the porous silicon in the first P doped silicon region. 
 
     
     
       11. The method of  claim 10 , wherein the first P doped silicon region fully surrounds the second N type silicon region except for a second surface of the second N type silicon region. 
     
     
       12. The method of  claim 10 , wherein the second N type silicon region has a first portion that overlaps the first P doped silicon region and a second portion that extends laterally beyond the first P doped silicon region. 
     
     
       13. The method of  claim 10 , further comprising:
 forming a second P doped silicon region within the second N type silicon region by doping with a P type impurity; 
 forming porous silicon in the second P doped silicon region by anodizing the second P doped silicon region; and 
 forming a second silicon oxide region by oxidizing the porous silicon in the second P doped silicon region together with the porous silicon in the first P doped silicon region. 
 
     
     
       14. The method of  claim 10 , wherein the oxidizing the porous silicon in the first P doped silicon region is under a temperature ranging from about 950° C. to about 1150° C. 
     
     
       15. The method of  claim 10 , wherein the anodizing the first P doped silicon region includes anodizing the first P doped silicon region using hydrofluoric acid. 
     
     
       16. The method of  claim 10 , further comprising removing an excess portion of the first silicon oxide region using hydrofluoric acid. 
     
     
       17. A method, comprising:
 forming a mask layer over an epitaxial N type semiconductor layer of a substrate; 
 forming a first aperture through the mask layer by patterning the mask layer; 
 forming a first P doped region by doping a P type impurity through the first aperture to a first depth; 
 forming a second aperture through the mask layer by patterning the mask layer; 
 forming a second P doped region and an extended first P doped region by doping the P type impurity through the first aperture and the second aperture together, the second P doped region including a second depth and the extended first P doped region including a third depth; 
 forming porous silicon in the extended first P doped region and the second P doped region by anodizing; and 
 forming a first silicon oxide region and a second silicon oxide region by oxidizing the porous silicon in the extended first P doped region and the second P doped region. 
 
     
     
       18. The method of  claim 17 , wherein the third depth equals to approximately an addition of the first depth and the second depth. 
     
     
       19. The method of  claim 17 , wherein oxidizing the porous silicon in the extended first P doped region and the second P doped region is under a temperature ranging from about 950° C. to about 1150° C. 
     
     
       20. The method of  claim 16 , further comprising forming a body region of a device, the body region being shallower than the first silicon oxide region.