Pulsing scheme for a ferroelectric memory bit-cell to minimize read or write disturb effect and refresh logic

Abstract

A memory is provided which comprises a capacitor including non-linear polar material. The capacitor may have a first terminal coupled to a node (e.g., a storage node) and a second terminal coupled to a plate-line. The capacitors can be a planar capacitor or non-planar capacitor (also known as pillar capacitor). The memory includes a transistor coupled to the node and a bit-line, wherein the transistor is controllable by a word-line, wherein the plate-line is parallel to the bit-line. The memory includes a refresh circuitry to refresh charge on the capacitor periodically or at a predetermined time. The refresh circuit can utilize one or more of the endurance mechanisms. When the plate-line is parallel to the bit-line, a specific read and write scheme may be used to reduce the disturb voltage for unselected bit-cells. A different scheme is used when the plate-line is parallel to the word-line.

We claim: 
     
       1. An apparatus comprising:
 a node; 
 a capacitor comprising non-linear polar material, the capacitor having a first terminal coupled to the node and a second terminal coupled to a plate-line, wherein the capacitor is a pillar capacitor; 
 a transistor coupled to the node and a bit-line, wherein the transistor is controllable by a word-line, wherein the plate-line is parallel to the bit-line; 
 a refresh circuitry to refresh charge on the capacitor periodically; and 
 one or more circuitries to boost the word-line above a voltage supply level during a write operation and a read operation, wherein the one or more circuitries is to generate a first pulse on the bit-line after the word-line is boosted and before an end of the boost on the word-line during a first write operation, and wherein the one or more circuitries is to generate a second pulse on the plate-line after the word-line is boosted and before the end of the boost on the word-line during a second write operation different from the first write operation. 
 
     
     
       2. The apparatus of  claim 1 , wherein the refresh circuitry comprises logic to improve memory endurance of the capacitor via wear leveling, and wherein the wear leveling is applied during read or write operations. 
     
     
       3. The apparatus of  claim 2 , wherein the wear leveling includes a random wear leveling scheme. 
     
     
       4. The apparatus of  claim 2 , the refresh circuitry is to apply an outlier compensation scheme before or after the wear leveling. 
     
     
       5. The apparatus of  claim 1 , wherein the one or more circuitries is to force a first voltage on the plate-line during the first write operation. 
     
     
       6. The apparatus of  claim 5 , wherein the one or more circuitries is to force the first voltage on the bit-line during the first write operation. 
     
     
       7. The apparatus of  claim 1 , wherein the one or more circuitries is to initially force a voltage on the bit-line and subsequently allow the bit-line to float during the read operation, wherein the one or more circuitries is to boost the word-line above the voltage supply level during the read operation. 
     
     
       8. The apparatus of  claim 7 , wherein the one or more circuitries is to generate a third pulse on the plate-line after the word-line is boosted and before an end of the boost on the word-line during the read operation. 
     
     
       9. The apparatus of  claim 1 , wherein the transistor is a low leakage transistor. 
     
     
       10. The apparatus of  claim 1  comprising a repeater coupled to the word-line. 
     
     
       11. The apparatus of  claim 1 , wherein the transistor is a first transistor, wherein the apparatus comprises a second transistor having a gate terminal coupled to the word-line, wherein the second terminal of the capacitor is coupled to the plate-line via the second transistor, wherein a source terminal of the second transistor is coupled to the plate-line, and wherein a drain terminal of the second transistor coupled to the second terminal of the capacitor. 
     
     
       12. The apparatus of  claim 1 , wherein when the capacitor comprises:
 a first layer comprising a first conducting material, wherein the first layer is coupled to the first terminal of the capacitor; 
 a second layer comprising a second conducting material, wherein the second layer is around the first layer; 
 a third layer comprising the non-linear polar material, wherein the third layer is around the second layer; 
 a fourth layer comprising the second conducting material, wherein the fourth layer is around the third layer; and 
 a fifth layer comprising the first conducting material, wherein the plate-line is partially coupled to the fifth layer. 
 
     
     
       13. The apparatus of  claim 12 , wherein the first layer has a first circumference, wherein the second layer has a second circumference, wherein the third layer has a third circumference, wherein the fourth layer has a fourth circumference, wherein the fifth layer has a fifth circumference, wherein the fourth circumference is larger than the third circumference, wherein the third circumference is larger than the second circumference, and wherein the second circumference is larger than the first circumference. 
     
     
       14. The apparatus of  claim 1 , wherein the non-linear polar material includes one of:
 Bismuth ferrite (BFO) with a doping material, wherein the doping material is one of Lanthanum, or elements from lanthanide series of periodic table; 
 Lead zirconium titanate (PZT), or PZT with a doping material, wherein the doping material is one of La or Nb; 
 a relaxor ferroelectric which includes one of lead magnesium niobate (PMN), lead magnesium niobate-lead titanate (PMN-PT), lead lanthanum zirconate titanate (PLZT), lead scandium niobate (PSN), Barium Titanium-Bismuth Zinc Niobium Tantalum (BT-BZNT), or Barium Titanium-Barium Strontium Titanium (BT-BST); 
 a perovskite which includes one of: BaTiO3, PbTiO3, KNbO3, or NaTaO3; 
 a hexagonal ferroelectric which includes one of: YMnO3 or LuFeO3; 
 hexagonal ferroelectrics of a type h-RMnO3, where R is a rare earth element which includes one of: cerium (Ce), dysprosium (Dy), erbium (Er), europium (Eu), gadolinium (Gd), holmium (Ho), lanthanum (La), lutetium (Lu), neodymium (Nd), praseodymium (Pr), promethium (Pm), samarium (Sm), scandium (Sc), terbium (Tb), thulium (Tm), ytterbium (Yb), or yttrium (Y); 
 Hafnium (Hf), Zirconium (Zr), Aluminum (Al), Silicon (Si), their oxides or their alloyed oxides; 
 Hafnium oxides as Hf1-x Ex Oy, where E cart be Al, Ca, Ce, Dy, Er, Gd, Ge, La, Sc, Si, Sr, Sn, or Y; 
 Al(1-x)Sc(x)N, Ga(1-x)Sc(x)N, Al(1-x)Y(x)N or Al(1-x-y)Mg(x)Nb(y)N, y doped HfO2, where x includes one of: Al, Ca, Ce, Dy, Er, Gd, Ge, La, Sc, Si, Sr, Sn, or Y, wherein ‘x’ is a fraction; 
 Niobate type compounds LiNbO3, LiTaO3, Lithium iron Tantalum Oxy Fluoride, Barium Strontium Niobate, Sodium Barium Niobate, or Potassium strontium niobate; or 
 an improper ferroelectric which includes one of: [PTO/STO]n or [LAO/STO]n, where ‘n’ is between 1 to 100. 
 
     
     
       15. An apparatus comprising:
 a node; 
 a capacitor comprising non-linear polar material, the capacitor having a first terminal coupled to the node and a second terminal coupled to a plate-line, wherein the capacitor is a planar capacitor; 
 a transistor coupled to the node and a bit-line, wherein the transistor is controllable by a word-line, wherein the plate-line is parallel to the bit-line; 
 a refresh circuitry to refresh charge on the capacitor periodically; and 
 one or more circuitries to boost the word-line above a voltage supply level during a write operation and a read operation, wherein the one or more circuitries is to generate a first pulse on the bit-line after the word-line is boosted and before an end of the boost on the word-line during a first write operation, and wherein the one or more circuitries is to generate a second pulse on the plate-line after the word-line is boosted and before the end of the boost on the word-line during a second write operation different from the first write operation. 
 
     
     
       16. The apparatus of  claim 15 , wherein the refresh circuitry comprises logic to improve memory endurance of the capacitor via wear leveling, and wherein the wear leveling is applied during read or write operations. 
     
     
       17. The apparatus of  claim 16 , wherein the wear leveling includes a random wear leveling scheme, and wherein the refresh circuitry is to apply an outlier compensation scheme before or after the wear leveling. 
     
     
       18. The apparatus of  claim 15 , wherein the planar capacitor comprises:
 a first layer coupled to a bottom electrode which is coupled to the node, wherein the first layer comprises a first refractive inter-metallic material, and wherein the first layer extends along an x-plane; 
 a second layer on the first layer, wherein the second layer comprises a first conductive oxide, and wherein the second layer extends along the x-plane; 
 a third layer comprising the non-linear polar material, wherein the third layer is on the second layer, and wherein the third layer extends along the x-plane; 
 a fourth layer on the third layer, wherein the fourth layer comprises a second conductive oxide, and wherein the fourth layer extends along the x-plane; and 
 a fifth layer on the fourth layer, wherein the fifth layer comprises a second refractive inter-metallic material, and wherein the plate-line is coupled to a portion of the fifth layer. 
 
     
     
       19. A system comprising:
 a processor circuitry to execute one or more instructions; 
 a memory to store the one or more instructions; and 
 a communication interface to allow the processor circuitry to communicate with another device, wherein the memory includes:
 a node; 
 a capacitor comprising non-linear polar material, the capacitor having a first terminal coupled to the node and a second terminal coupled to a plate-line, wherein the capacitor is a pillar capacitor; 
 a transistor coupled to the node and a bit-line, wherein the transistor is controllable by a word-line, wherein the plate-line is parallel to the bit-line; 
 a refresh circuitry to refresh charge on the capacitor periodically; and 
 one or more circuitries to boost the word-line above a voltage supply level during a write operation and a read operation, wherein the one or more circuitries is to generate a first pulse on the bit-line after the word-line is boosted and before an end of the boost on the word-line during a first write operation, and wherein the one or more circuitries is to generate a second pulse on the plate-line after the word-line is boosted and before the end of the boost on the word-line during a second write operation different from the first write operation. 
 
 
     
     
       20. The system of  claim 19 , wherein the refresh circuitry comprises logic to improve memory endurance of the capacitor via wear leveling, and wherein the wear leveling is applied during read or write operations to the memory.