Performance silicon carbide power devices

Abstract

A device is described herein. The device comprises a unit cell of a silicon carbide (SiC) substrate. The unit cell comprises: a trench in a well region having a second conduction type. The well region is in contact with a region having a first conduction type to form a p-n junction. A width of the trench is less than 1.0 micrometers (μm). A width of the unit cell is one of less than and equal to 5.0 micrometers (μm). The device comprises a source region comprising the first conduction type. The device further comprises a metal oxide semiconductor field effect transistor component. The device described herein comprises a reduced unit cell pitch and reduced channel resistance without any compromise in channel length. The device comprises an ILD opening greater than or equal to width of the trench.

What is claimed is: 
     
       1. A Silicon Carbide (SiC) metal-oxide-semiconductor field-effect transistor (MOSFET) device comprising a unit cell, the unit cell comprising: a source region formed within a well region, and
 a second conductivity type sinker region located below the source region; and 
 wherein a unit cell pitch is one of less than and equal to 5.0 micrometers (μm), 
 wherein a lateral spacing between the adjacent well regions is one of less than and equal to 1.5 micrometers, 
 wherein the SiC MOSFET device comprises a drain to source breakdown voltage less than 1700 Volts, and 
 wherein a first on-resistance measured at 175° C. on the SiC MOSFET device is less than 1.6 times a second on-resistance measured at 25° C. 
 
     
     
       2. The SiC MOSFET device of  claim 1 , wherein a MOSFET channel length is larger than 0.2 micrometers (μm). 
     
     
       3. The SiC MOSFET device of  claim 1 , wherein the SiC MOSFET device comprises a third on-resistance of less than 4 milliohm centimeter squared and a short-circuit withstand time of greater than 2.0 microseconds at a direct current (DC) link voltage of 800 volts. 
     
     
       4. The SiC MOSFET device of  claim 1 , further comprising a second conductivity type plug region. 
     
     
       5. The SiC MOSFET device of  claim 4 , wherein the second conductivity type plug region is formed after formation of a trench region formed inside the well region, wherein the trench region has a depth that is greater than a thickness of the source region. 
     
     
       6. The SiC MOSFET device of  claim 5 , wherein a first width of the trench region is less than 1.2 micrometers (μm). 
     
     
       7. The SiC MOSFET device of  claim 6 , wherein the trench regions are formed periodically in a direction orthogonal to a second width of the unit cell. 
     
     
       8. The SiC MOSFET device of  claim 7 , wherein the period of the trench regions are 3.0 micrometers. 
     
     
       9. The SiC MOSFET device of  claim 5 , wherein an opening in an interlevel dielectric (ILD) layer is equal to a first width of the trench region. 
     
     
       10. A Silicon Carbide (SiC) metal-oxide-semiconductor field-effect transistor (MOSFET) device comprising a unit cell, the unit cell comprising: a source region formed within a well region, and
 a second conductivity type sinker region located below the source region; and 
 wherein a unit cell pitch is one of less than and equal to 5.0 micrometers (μm), 
 wherein a lateral spacing between the adjacent well regions is one of less than and equal to 1.5 micrometers, 
 wherein the SiC MOSFET device comprises a breakdown voltage less than 1000 Volts, and 
 wherein a first on-resistance measured at 175° C. on the SiC MOSFET device is less than 1.3 times a second on-resistance measured at 25° C. 
 
     
     
       11. The SiC MOSFET device of  claim 10 , wherein a MOSFET channel length is larger than 0.2 micrometers (μm). 
     
     
       12. The SiC MOSFET device of  claim 10 , wherein the SiC MOSFET device comprises a third on-resistance of less than 4 milliohm centimeter squared and a short-circuit withstand time of greater than 2.0 microseconds at a direct current (DC) link voltage of 400 volts. 
     
     
       13. The SiC MOSFET device of  claim 10 , further comprising a second conductivity type plug region. 
     
     
       14. The SiC MOSFET device of  claim 13 , wherein the second conductivity type plug region is formed after formation of a trench region formed inside the well region, wherein the trench region has a depth that is greater than a thickness of the source region. 
     
     
       15. The SiC MOSFET device of  claim 14 , wherein a first width of the trench region is less than 1.2 micrometers (μm). 
     
     
       16. The SiC MOSFET device of  claim 15 , wherein the trench regions are formed periodically in a direction orthogonal to a second width of the unit cell. 
     
     
       17. The SiC MOSFET device of  claim 16 , wherein the period of the trench regions are 3.0 micrometers. 
     
     
       18. The SiC MOSFET device of  claim 14 , wherein an opening in an interlevel dielectric (ILD) layer is equal to a first width of the trench region.