Pulse width modulation circuit with reduced minimum on-time

Abstract

A pulse width modulator PWM circuit and a corresponding method are presented. The PWM circuit receives a control signal and a clock signal. The PWM circuit generates an output signal based on the control signal and the clock signal. The output signal has a first or second signal value. The PWM circuit has a delay circuit to generate, by delaying the clock signal by a delay period, a first enable signal for setting the output signal to the first signal value. The PWM circuit has a ramp generator to generate a ramp signal based on the clock signal. The PWM circuit has a comparator to generate, by comparing the control signal with the ramp signal, a second enable signal for setting the output signal to the second signal value. By delaying the clock signal by the delay period, a minimum on-time of the output signal may be reduced.

What is claimed is: 
     
       1. A pulse width modulator PWM circuit configured to receive a control signal and a clock signal, and to generate an output signal based on said control signal and said clock signal, wherein the output signal has a first signal value or a second signal value, wherein the PWM circuit comprises
 a delay circuit configured to generate, by delaying the clock signal by a delay period, a first enable signal for setting the output signal to the first signal value; 
 a ramp generator configured to generate a ramp signal based on the clock signal; and 
 a comparator configured to generate, by comparing the control signal with the ramp signal, a second enable signal for setting the output signal to the second signal value, 
 
       wherein the ramp generator comprises a release input, wherein the clock signal is applied to said release input, and wherein the ramp generator is configured to generate the ramp signal such that the ramp signal
 has an initial signal value until a signal change of the clock signal occurs at the release input, and such that the ramp signal 
 starts increasing or decreasing with a constant slope responsive to the signal change of the clock signal; and 
 
       wherein the PWM circuit further comprises a second flip-flop, wherein
 the second enable signal is coupled to a first input of the second flip-flop, 
 the clock signal is coupled to a second input of the second flip-flop, and 
 an output of the second flip-flop is coupled to a reset input of the ramp generator. 
 
     
     
       2. The PWM circuit of  claim 1 , further comprising a first flip-flop configured to generate the output signal based on the first enable signal and the second enable signal. 
     
     
       3. The PWM circuit of  claim 1 , wherein the delay period is equal to or larger than a delay of the comparator. 
     
     
       4. The PWM circuit of  claim 1 , wherein the ramp generator is configured to generate the ramp signal such that the ramp signal returns to said initial signal value when a signal change occurs at the reset input of the ramp generator. 
     
     
       5. A power converter comprising a pass device and the PWM circuit of  claim 1 , wherein the output signal of the PWM circuit is applied to a control input of the pass device for controlling a current flow through said pass device. 
     
     
       6. A method of operating a pulse width modulator PWM circuit for generating an output signal based on a control signal and a clock signal, wherein the output signal has a first signal value or a second signal value, wherein the PWM circuit comprises a delay circuit, a ramp generator, and a comparator, wherein the method comprises
 generating, by the delay circuit, by delaying the clock signal by a delay period, a first enable signal for setting the output signal to the first signal value; 
 generating, by the ramp generator, a ramp signal based on the clock signal; and 
 generating, by the comparator, by comparing the control signal with the ramp signal, a second enable signal for setting the output signal to the second signal value, 
 
       wherein the ramp generator comprises a release input, wherein the clock signal is applied to said release input, and wherein the method comprises generating, by the ramp generator, the ramp signal such that the ramp signal
 has an initial signal value until a signal change of the clock signal occurs at the release input, and 
 starts increasing or decreasing with a constant slope responsive to the signal change of the clock signal; and 
 
       wherein the PWM circuit further comprises a second flip-flop, wherein the method comprises
 coupling the second enable signal to a first input of the second flip-flop, 
 coupling the clock signal to a second input of the second flip-flop, and 
 coupling an output of the second flip-flop to a reset input of the ramp generator. 
 
     
     
       7. The method of  claim 6 , further comprising
 generating, by a first flip-flop, the output signal based on the first enable signal and the second enable signal. 
 
     
     
       8. The method of  claim 6 , wherein the delay period is equal to or larger than a delay of the comparator. 
     
     
       9. The method of  claim 6 , wherein the method comprises
 generating, by the ramp generator, the ramp signal such that the ramp signal returns to said initial signal value when a signal change occurs at said reset input. 
 
     
     
       10. The method of  claim 6 , wherein the method comprises
 applying the output signal of the PWM circuit to a control input of a pass device of a power converter for controlling a current flow through said pass device.