Seamlessly integrated microcontroller chip

Abstract

Techniques in electronic systems, such as in systems comprising a CPU die and one or more external mixed-mode (analog) chips, may provide improvements advantages in one or more of system design, performance, cost, efficiency and programmability. In one embodiment, the CPU die comprises at least one microcontroller CPU and circuitry enabling the at least one CPU to have a full and transparent connectivity to an analog chip as if they are designed as a single chip microcontroller, while the interface design between the two is extremely efficient and with limited in number of wires, yet may provide improved performance without impact to functionality or the software model.

What is claimed is: 
     
       1. A system, comprising:
 a first die with a central processing unit (CPU) and a first bridge; 
 a second die with a second bridge, wherein the second die excludes a second CPU or that has a third CPU unrelated to the first bridge and the second bridge; and 
 die-to-die interconnects electrically coupled to the first bridge and the second bridge, wherein the die-to-die interconnects comprise fewer signal lines than a first bus in the first die and a second bus in the second die, 
 wherein the first bridge and the second bridge are configured to mask existence of the die-to-die interconnects, so that a function of the second die appears as though it is implemented on the first die to a master on the first die, and 
 wherein the second bridge is configured to pause a transaction by a bus master on the first die to allow a transaction by a second bus master on the second die to occur via the die-to-die interconnects prior to finalizing the paused transaction by the first bus master. 
 
     
     
       2. The system of  claim 1 , wherein the master comprises the CPU. 
     
     
       3. The system of  claim 1 , wherein the first die comprises multiple devices, one or more of which is configured to act as a bus master that is configured to engage in bus transactions to bus slaves on the second die via the die-to-die interconnects. 
     
     
       4. The system of  claim 1 , wherein the second die comprises multiple devices, one or more of which is configured to act as a bus slave with respect to the first bridge and the second bridge. 
     
     
       5. The system of  claim 1 , wherein the first die is configured to provide a single wider bandwidth connection via the die-to-die interconnects when only a single instance of the second die is implemented, while allowing two lower bandwidth connections via the die-to-die interconnects for implementations where there are two instances of the second die. 
     
     
       6. The system of  claim 1 , wherein a software model implemented on the first die is the same as if it was implemented on a single-die system. 
     
     
       7. The system of  claim 1 , wherein the first bus and the second bus have a common format. 
     
     
       8. The system of  claim 7 , wherein the format comprises: an ARM Advanced Microcontroller Bus Architecture (AMBA) Advanced High-Performance Bus (AHB), AHBLite or AHBS. 
     
     
       9. The system of  claim 7 , wherein the format comprises a Wishbone architecture. 
     
     
       10. The system of  claim 1 , further comprising:
 a second bus master on the second die electrically coupled to a third bus on the second die and a third bridge electrically coupled to the third bus as a bus slave; 
 a second bus slave on the first die electrically coupled to a fourth bus on the first die, and a fourth bridge electrically coupled to the fourth bus as a bus master; and 
 second die-to-die interconnects configured to convey second signals between the third bridge and the fourth bridge, wherein a number of the second die-to-die interconnects is less than a number of signal lines between the second bus master and the third bridge, and 
 wherein the first bridge, the second bridge, and the die-to-die interconnects are configured to enable the bus master to engage in bus transactions with the bus slave in the same manner as if the bus transactions occurred in a single-die system. 
 
     
     
       11. The system of  claim 10 , wherein CPU instructions for accessing the bus slave on the second die are the same as if the bus slave was implemented on the first die. 
     
     
       12. A method of communicating between a first die with a first bridge and second die with a second bridge, comprising:
 receiving, at the first bridge, signals from a central processing unit (CPU) in the first die that correspond to a function of the second die; 
 communicating, to the second bridge, the signals via die-to-die interconnects electrically coupled to the first bridge and the second bridge, wherein the die-to-die interconnects comprise fewer signal lines than a first bus in the first die and a second bus in the second die, 
 wherein, when communicating the signals, the first bridge and the second bridge mask existence of the die-to-die interconnects, so that the function of the second die appears as though it is implemented on the first die to a master on the first die, and 
 wherein the second die excludes a second CPU or that has a third CPU unrelated to the first bridge and the second bridge; and 
 pausing, by the second bridge, a transaction by a bus master on the first die to allow a transaction by a second bus master on the second die to occur via the die-to-die interconnects prior to finalizing the paused transaction by the first bus master. 
 
     
     
       13. The method of  claim 12 , wherein the master comprises the CPU. 
     
     
       14. The method of  claim 12 , wherein the first die comprises multiple devices, one or more of which act as a bus master that engages in bus transactions to bus slaves on the second die via the die-to-die interconnects. 
     
     
       15. The method of  claim 12 , wherein the second die comprises multiple devices, one or more of which acts as a bus slave with respect to the first bridge and the second bridge. 
     
     
       16. The method of  claim 12 , wherein the first die provides a single wider bandwidth interconnects when only a single instance of the second die is implemented, while allowing two lower bandwidth connections for implementations where there are two instances of the second die. 
     
     
       17. The method of  claim 12 , wherein a software model implemented on the first die is the same as if it was implemented on a single-die system. 
     
     
       18. An electronic device, comprising:
 a first die with a central processing unit (CPU) and a first bridge; 
 a second die with a second bridge, wherein the second die excludes a second CPU or that has a third CPU unrelated to the first bridge and the second bridge; and 
 die-to-die interconnects electrically coupled to the first bridge and the second bridge, wherein the die-to-die interconnects comprise fewer signal lines than a first bus in the first die and a second bus in the second die, 
 wherein the first bridge and the second bridge are configured to mask existence of the die-to-die interconnects, so that a function of the second die appears as though it is implemented on the first die to a master on the first die, and 
 wherein the second bridge is configured to pause a transaction by a bus master on the first die to allow a transaction by a second bus master on the second die to occur via the die-to-die interconnects prior to finalizing the paused transaction by the first bus master.