Low noise amplifier circuit for a thermal varying resistance

Abstract

A circuit arrangement, including: a circuit configured to synthesize a resistor having a resistance value having a variation in time equivalent to a resistance variation of a sensor resistor applied with a resistance bias voltage and a resistance current bias, wherein the circuit includes: an amplifier comprising an input transistor; a bias current generator comprising a control node coupled to an output of the input transistor, wherein the bias current generator is configured to generate a bias current flowing in the input transistor; and a further current generator configured to generate a current at least proportional to the resistance bias current and coupled to the output of the input transistor, wherein the resistance bias voltage is applied to an input of the amplifier, and wherein a transconductance of the input transistor is at least proportional to the resistance of the sensor resistor.

What is claimed is: 
     
       1. A circuit, an input of the circuit coupled to a sense resistor at a first sense terminal and a second sense terminal, the circuit comprising:
 a first amplifier circuit, the first amplifier circuit comprising a first transistor, a first load resistor, a first capacitor, and a first current generator, the first transistor configured as a first common gate amplifier, a first current path terminal of the first transistor coupled to a first supply voltage terminal through the first load resistor, a second current path terminal of the first transistor coupled to the first sense terminal and a second supply voltage terminal, a control terminal of the first transistor coupled to a first bias voltage terminal and the first capacitor, the first capacitor configured as a low band filter; and 
 a second amplifier circuit, the second amplifier circuit comprising a second transistor, a second load resistor, a second capacitor, and a second current generator, the second transistor configured as a second common gate amplifier, a first current path terminal of the second transistor coupled to the first supply voltage terminal through the second load resistor, a second current path terminal of the second transistor coupled to the second sense terminal and the second supply voltage terminal, a control terminal of the second transistor coupled to a second bias voltage terminal and the second capacitor, the second capacitor configured as a low band filter. 
 
     
     
       2. The circuit of  claim 1 , wherein the sense resistor is a thermal varying resistor, a resistance of the thermal varying resistor changing based on a change in temperature at the thermal varying resistor. 
     
     
       3. The circuit of  claim 1 , further comprising a positive supply voltage and a negative supply voltage, the first voltage supply terminal coupled to the positive supply voltage, and the second supply voltage terminal coupled to the negative supply voltage. 
     
     
       4. The circuit of  claim 1 , further comprising a positive bias voltage supply and a negative bias voltage supply, the first bias voltage terminal coupled to the negative bias voltage supply, and the second bias voltage terminal coupled to the positive bias voltage supply. 
     
     
       5. The circuit of  claim 4 , wherein the first amplifier circuit further comprises a first control circuit, wherein the second amplifier circuit further comprises a second control circuit, the first control circuit configured to selectively apply the negative bias voltage supply to the first transistor, and the second control circuit configured to selectively apply the positive bias voltage supply to the second transistor. 
     
     
       6. The circuit of  claim 1 , wherein the first amplifier circuit further comprises an amplifier configured to compare a voltage on the first load resistor to a reference voltage, and, based thereon, adjust a current value generated by the first current generator. 
     
     
       7. The circuit of  claim 1 , wherein the second amplifier circuit further comprises an amplifier configured to compare a voltage on the second load resistor to a reference voltage, and, based thereon, adjust a current value generated by the second current generator. 
     
     
       8. The circuit of  claim 1 , wherein each of the first transistor and the second transistor is a differential amplifier. 
     
     
       9. The circuit of  claim 1 , wherein the circuit is arranged in a hard disk drive, the circuit configured to perform sensing and control of fly height of a tip in the hard disk drive. 
     
     
       10. A hard disk drive, comprising:
 a thermal resistor configured to perform sensing and control of fly height of a tip in the hard disk drive, the thermal resistor having a first sense terminal and a second sense terminal; and 
 a circuit configured to synthesize the thermal resistor, the circuit comprising:
 a first amplifier circuit, the first amplifier circuit comprising a first transistor, a first load resistor, a first capacitor, and a first current generator, the first transistor configured as a first common gate amplifier, a first current path terminal of the first transistor coupled to a first supply voltage terminal through the first load resistor, a second current path terminal of the first transistor coupled to the first sense terminal and a second supply voltage terminal, a control terminal of the first transistor coupled to a first bias voltage terminal and the first capacitor, the first capacitor configured as a low band filter, and 
 a second amplifier circuit, the second amplifier circuit comprising a second transistor, a second load resistor, a second capacitor, and a second current generator, the second transistor configured as a second common gate amplifier, a first current path terminal of the second transistor coupled to the first supply voltage terminal through the second load resistor, a second current path terminal of the second transistor coupled to the second sense terminal and the second supply voltage terminal, a control terminal of the second transistor coupled to a second bias voltage terminal and the second capacitor, the second capacitor configured as a low band filter. 
 
 
     
     
       11. The hard disk drive of  claim 10 , wherein the circuit further comprises a positive supply voltage and a negative supply voltage, the first voltage supply terminal coupled to the positive supply voltage, and the second supply voltage terminal coupled to the negative supply voltage. 
     
     
       12. The hard disk drive of  claim 10 , wherein the circuit further comprises a positive bias voltage supply and a negative bias voltage supply, the first bias voltage terminal coupled to the negative bias voltage supply, and the second bias voltage terminal coupled to the positive bias voltage supply. 
     
     
       13. The hard disk drive of  claim 12 , wherein the first amplifier circuit further comprises a first control circuit, wherein the second amplifier circuit further comprises a second control circuit, the first control circuit configured to selectively apply the negative bias voltage supply to the first transistor, and the second control circuit configured to selectively apply the positive bias voltage supply to the second transistor. 
     
     
       14. The hard disk drive of  claim 10 , wherein the first amplifier circuit further comprises an amplifier configured to compare a voltage on the first load resistor to a reference voltage, and, based thereon, adjust a current value generated by the first current generator. 
     
     
       15. The hard disk drive of  claim 10 , wherein the second amplifier circuit further comprises an amplifier configured to compare a voltage on the second load resistor to a reference voltage, and, based thereon, adjust a current value generated by the second current generator. 
     
     
       16. The hard disk drive of  claim 10 , wherein each of the first transistor and the second transistor is a differential amplifier. 
     
     
       17. A method for operating a circuit used to perform sensing and control of a fly height type in a hard disk drive through a sense resistor, the method comprising:
 having a first amplifier circuit, the first amplifier circuit comprising a first transistor, a first load resistor, a first capacitor, and a first current generator, the first transistor configured as a first common gate amplifier, a first current path terminal of the first transistor coupled to a first supply voltage terminal through the first load resistor, a second current path terminal of the first transistor coupled to a first sense terminal of the sense resistor and a second supply voltage terminal, a control terminal of the first transistor coupled to a first bias voltage terminal and the first capacitor, the first capacitor configured as a low band filter, the sense resistor; 
 having a second amplifier circuit, the second amplifier circuit comprising a second transistor, a second load resistor, a second capacitor, and a second current generator, the second transistor configured as a second common gate amplifier, a first current path terminal of the second transistor coupled to the first supply voltage terminal through the second load resistor, a second current path terminal of the second transistor coupled to a second sense terminal of the sense resistor and the second supply voltage terminal, a control terminal of the second transistor coupled to a second bias voltage terminal and the second capacitor, the second capacitor configured as a low band filter; 
 applying a constant voltage to the sense resistor corresponding to a selection of a voltage mode operation of the circuit; 
 applying a constant current to the sense resistor based on a selection of a current mode operation of the circuit; and 
 amplifying, using the first amplifier circuit and the second amplifier circuit, input signals from the sense resistor in accordance with a variation in resistance at the sense resistor. 
 
     
     
       18. The method of  claim 17 , further comprising filtering the input signals using a high pass filter. 
     
     
       19. The method of  claim 17 , further comprising filtering the input signals using a low pass filter. 
     
     
       20. The method of  claim 17 , further comprising biasing each of the first transistor and the second transistor, wherein the biasing and the amplifying are performed at a same stage of operation.